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Apollo4p Register Documentation R4.4.1
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Apollo4p Register Documentation R4.4.1
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| Instance 0 Address: | 0x40010000 |
Controls the operation of GPIO pin 0.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN0
0x0 |
FIEN0
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL0
0x0 |
NCESRC0
0x0 |
PULLCFG0
0x0 |
SR0
0x0 |
DS0
0x0 |
OUTCFG0
0x0 |
IRPTEN0
0x0 |
RDZERO0
0x0 |
INPEN0
0x0 |
FNCSEL0
0x3 |
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| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN0 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN0 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL0 | RW | Polarity select for NCE for GPIO 0 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC0 | RW | IOMSTR/MSPI N Chip Select 0, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG0 | RW | Pullup/Pulldown configuration for GPIO 0 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR0 | RW | Configure the slew rate |
| 11:10 | DS0 | RW | Drive strength selection for GPIO 0 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG0 | RW | Pin IO mode selection for GPIO pin 0 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN0 | RW | Interrupt enable for GPIO 0 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO0 | RW | Return 0 for read data on GPIO 0 |
| 4 | INPEN0 | RW | Input enable for GPIO 0 |
| 3:0 | FNCSEL0 | RW | Function select for GPIO pin 0 SWTRACECLK = 0x0 - Serial Wire Debug Trace Clock SLSCL = 0x1 - I2C Slave clock SLSCK = 0x2 - SPI Slave clock GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) UART1TX = 0x5 - UART transmit output (UART 1) CT0 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE0 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS0 = 0x8 - Observation bus bit 0 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010004 |
Controls the operation of GPIO pin 1.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN1
0x0 |
FIEN1
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL1
0x0 |
NCESRC1
0x0 |
PULLCFG1
0x0 |
SR1
0x0 |
DS1
0x0 |
OUTCFG1
0x0 |
IRPTEN1
0x0 |
RDZERO1
0x0 |
INPEN1
0x0 |
FNCSEL1
0x3 |
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| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN1 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN1 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL1 | RW | Polarity select for NCE for GPIO 1 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC1 | RW | IOMSTR/MSPI N Chip Select 1, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG1 | RW | Pullup/Pulldown configuration for GPIO 1 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR1 | RW | Configure the slew rate |
| 11:10 | DS1 | RW | Drive strength selection for GPIO 1 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG1 | RW | Pin IO mode selection for GPIO pin 1 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN1 | RW | Interrupt enable for GPIO 1 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO1 | RW | Return 0 for read data on GPIO 1 |
| 4 | INPEN1 | RW | Input enable for GPIO 1 |
| 3:0 | FNCSEL1 | RW | Function select for GPIO pin 1 SWTRACE0 = 0x0 - Serial Wire Debug Trace Output 0 SLSDAWIR3 = 0x1 - I2C Slave I/O data (I2C) 3 Wire Data (SPI) SLMOSI = 0x2 - SPI Slave input data GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) UART3TX = 0x5 - UART transmit output (UART 3) CT1 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE1 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS1 = 0x8 - Observation bus bit 1 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANIN4 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010008 |
Controls the operation of GPIO pin 2.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN2
0x0 |
FIEN2
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL2
0x0 |
NCESRC2
0x0 |
PULLCFG2
0x0 |
SR2
0x0 |
DS2
0x0 |
OUTCFG2
0x0 |
IRPTEN2
0x0 |
RDZERO2
0x0 |
INPEN2
0x0 |
FNCSEL2
0x3 |
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| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN2 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN2 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL2 | RW | Polarity select for NCE for GPIO 2 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC2 | RW | IOMSTR/MSPI N Chip Select 2, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG2 | RW | Pullup/Pulldown configuration for GPIO 2 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR2 | RW | Configure the slew rate |
| 11:10 | DS2 | RW | Drive strength selection for GPIO 2 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG2 | RW | Pin IO mode selection for GPIO pin 2 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN2 | RW | Interrupt enable for GPIO 2 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO2 | RW | Return 0 for read data on GPIO 2 |
| 4 | INPEN2 | RW | Input enable for GPIO 2 |
| 3:0 | FNCSEL2 | RW | Function select for GPIO pin 2 SWTRACE1 = 0x0 - Serial Wire Debug Trace Output 1 SLMISO = 0x1 - SPI Slave output data TRIG1 = 0x2 - ADC trigger input GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) UART1RX = 0x5 - UART receive input (UART 1) CT2 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE2 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS2 = 0x8 - Observation bus bit 2 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANRSTN = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x4001000C |
Controls the operation of GPIO pin 3.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN3
0x0 |
FIEN3
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL3
0x0 |
NCESRC3
0x0 |
PULLCFG3
0x0 |
SR3
0x0 |
DS3
0x0 |
OUTCFG3
0x0 |
IRPTEN3
0x0 |
RDZERO3
0x0 |
INPEN3
0x0 |
FNCSEL3
0x3 |
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| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN3 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN3 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL3 | RW | Polarity select for NCE for GPIO 3 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC3 | RW | IOMSTR/MSPI N Chip Select 3, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG3 | RW | Pullup/Pulldown configuration for GPIO 3 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR3 | RW | Configure the slew rate |
| 11:10 | DS3 | RW | Drive strength selection for GPIO 3 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG3 | RW | Pin IO mode selection for GPIO pin 3 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN3 | RW | Interrupt enable for GPIO 3 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO3 | RW | Return 0 for read data on GPIO 3 |
| 4 | INPEN3 | RW | Input enable for GPIO 3 |
| 3:0 | FNCSEL3 | RW | Function select for GPIO pin 3 SWTRACE2 = 0x0 - Serial Wire Debug Trace Output 2 SLnCE = 0x1 - SPI Slave chip enable SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) UART3RX = 0x5 - UART receive input (UART 3) CT3 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE3 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS3 = 0x8 - Observation bus bit 3 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANIN5 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010010 |
Controls the operation of GPIO pin 4.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN4
0x0 |
FIEN4
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL4
0x0 |
NCESRC4
0x0 |
PULLCFG4
0x0 |
SR4
0x0 |
DS4
0x0 |
OUTCFG4
0x0 |
IRPTEN4
0x0 |
RDZERO4
0x0 |
INPEN4
0x0 |
FNCSEL4
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN4 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN4 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL4 | RW | Polarity select for NCE for GPIO 4 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC4 | RW | IOMSTR/MSPI N Chip Select 4, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG4 | RW | Pullup/Pulldown configuration for GPIO 4 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR4 | RW | Configure the slew rate |
| 11:10 | DS4 | RW | Drive strength selection for GPIO 4 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG4 | RW | Pin IO mode selection for GPIO pin 4 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN4 | RW | Interrupt enable for GPIO 4 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO4 | RW | Return 0 for read data on GPIO 4 |
| 4 | INPEN4 | RW | Input enable for GPIO 4 |
| 3:0 | FNCSEL4 | RW | Function select for GPIO pin 4 SWTRACE3 = 0x0 - Serial Wire Debug Trace Output 3 SLINT = 0x1 - Configurable Slave Interrupt 32KHzXT = 0x2 - 32kHZ from analog GPIO = 0x3 - General purpose I/O UART0RTS = 0x4 - UART Request to Send (RTS) (UART 0) UART1RTS = 0x5 - UART Request to Send (RTS) (UART 1) CT4 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE4 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS4 = 0x8 - Observation bus bit 4 I2S0_SDIN = 0x9 - I2S Data input (I2S Master/Slave 2) I2S1_SDIN = 0xA - I2S Data input (I2S Master/Slave 2) FPIO = 0xB - Fast PIO FLB_TDO = 0xC - Internal function (Flash Bist) FLLOAD_DIR = 0xD - Internal function (Flash parallel load) MDA_TDO = 0xE - Internal function (MBIST) OPCG_TRIG = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010014 |
Controls the operation of GPIO pin 5.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN5
0x0 |
FIEN5
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL5
0x0 |
NCESRC5
0x0 |
PULLCFG5
0x0 |
SR5
0x0 |
DS5
0x0 |
OUTCFG5
0x0 |
IRPTEN5
0x0 |
RDZERO5
0x0 |
INPEN5
0x0 |
FNCSEL5
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN5 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN5 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL5 | RW | Polarity select for NCE for GPIO 5 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC5 | RW | IOMSTR/MSPI N Chip Select 5, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG5 | RW | Pullup/Pulldown configuration for GPIO 5 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR5 | RW | Configure the slew rate |
| 11:10 | DS5 | RW | Drive strength selection for GPIO 5 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG5 | RW | Pin IO mode selection for GPIO pin 5 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN5 | RW | Interrupt enable for GPIO 5 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO5 | RW | Return 0 for read data on GPIO 5 |
| 4 | INPEN5 | RW | Input enable for GPIO 5 |
| 3:0 | FNCSEL5 | RW | Function select for GPIO pin 5 M0SCL = 0x0 - Serial I2C Master Clock output (IOM 0) M0SCK = 0x1 - Serial SPI Master Clock output (IOM 0) I2S0_CLK = 0x2 - Bidirectional I2S Bit clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART2RTS = 0x4 - UART Request to Send (RTS) (UART 2) UART3RTS = 0x5 - UART Request to Send (RTS) (UART 3) CT5 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE5 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS5 = 0x8 - Observation bus bit 5 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. I2S1_CLK = 0xA - Bidirectional I2S Bit clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) FPIO = 0xB - Fast PIO FLB_TDI = 0xC - Internal function (Flash Bist) FLLOAD_DATA = 0xD - Internal function (Flash parallel load) MDA_SRST = 0xE - Internal function (MBIST) DFT_ISO = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010018 |
Controls the operation of GPIO pin 6.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN6
0x0 |
FIEN6
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL6
0x0 |
NCESRC6
0x0 |
PULLCFG6
0x0 |
SR6
0x0 |
DS6
0x0 |
OUTCFG6
0x0 |
IRPTEN6
0x0 |
RDZERO6
0x0 |
INPEN6
0x0 |
FNCSEL6
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN6 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN6 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL6 | RW | Polarity select for NCE for GPIO 6 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC6 | RW | IOMSTR/MSPI N Chip Select 6, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG6 | RW | Pullup/Pulldown configuration for GPIO 6 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR6 | RW | Configure the slew rate |
| 11:10 | DS6 | RW | Drive strength selection for GPIO 6 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG6 | RW | Pin IO mode selection for GPIO pin 6 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN6 | RW | Interrupt enable for GPIO 6 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO6 | RW | Return 0 for read data on GPIO 6 |
| 4 | INPEN6 | RW | Input enable for GPIO 6 |
| 3:0 | FNCSEL6 | RW | Function select for GPIO pin 6 M0SDAWIR3 = 0x0 - Serial I2C Master Data I/O (I2C Mode) Serial SPI Master Data I/O (SPI 3 wire mode) (IOM 0) M0MOSI = 0x1 - Serial SPI Master MOSI output (IOM 0) I2S0_DATA = 0x2 - Bidirectional I2S Data. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART0CTS = 0x4 - UART Clear to Send (CTS) (UART 0) UART1CTS = 0x5 - UART Clear to Send (CTS) (UART 1) CT6 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE6 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS6 = 0x8 - Observation bus bit 6 I2S0_SDOUT = 0x9 - I2S Data output (I2S Master/Slave 2) I2S1_SDOUT = 0xA - I2S Data output (I2S Master/Slave 2) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANIN6 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x4001001C |
Controls the operation of GPIO pin 7.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN7
0x0 |
FIEN7
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL7
0x0 |
NCESRC7
0x0 |
PULLCFG7
0x0 |
SR7
0x0 |
DS7
0x0 |
OUTCFG7
0x0 |
IRPTEN7
0x0 |
RDZERO7
0x0 |
INPEN7
0x0 |
FNCSEL7
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN7 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN7 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL7 | RW | Polarity select for NCE for GPIO 7 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC7 | RW | IOMSTR/MSPI N Chip Select 7, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG7 | RW | Pullup/Pulldown configuration for GPIO 7 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR7 | RW | Configure the slew rate |
| 11:10 | DS7 | RW | Drive strength selection for GPIO 7 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG7 | RW | Pin IO mode selection for GPIO pin 7 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN7 | RW | Interrupt enable for GPIO 7 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO7 | RW | Return 0 for read data on GPIO 7 |
| 4 | INPEN7 | RW | Input enable for GPIO 7 |
| 3:0 | FNCSEL7 | RW | Function select for GPIO pin 7 M0MISO = 0x0 - Serial SPI MASTER MISO input (IOM 0) TRIG0 = 0x1 - ADC trigger input I2S0_WS = 0x2 - Bidirectional I2S L/R clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART2CTS = 0x4 - UART Clear to Send (CTS) (UART 2) UART3CTS = 0x5 - UART Clear to Send (CTS) (UART 3) CT7 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE7 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS7 = 0x8 - Observation bus bit 7 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. I2S1_WS = 0xA - Bidirectional I2S L/R clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANIN7 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010020 |
Controls the operation of GPIO pin 8.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN8
0x0 |
FIEN8
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL8
0x0 |
NCESRC8
0x0 |
PULLCFG8
0x0 |
SR8
0x0 |
DS8
0x0 |
OUTCFG8
0x0 |
IRPTEN8
0x0 |
RDZERO8
0x0 |
INPEN8
0x0 |
FNCSEL8
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN8 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN8 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL8 | RW | Polarity select for NCE for GPIO 8 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC8 | RW | IOMSTR/MSPI N Chip Select 8, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG8 | RW | Pullup/Pulldown configuration for GPIO 8 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR8 | RW | Configure the slew rate |
| 11:10 | DS8 | RW | Drive strength selection for GPIO 8 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG8 | RW | Pin IO mode selection for GPIO pin 8 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN8 | RW | Interrupt enable for GPIO 8 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO8 | RW | Return 0 for read data on GPIO 8 |
| 4 | INPEN8 | RW | Input enable for GPIO 8 |
| 3:0 | FNCSEL8 | RW | Function select for GPIO pin 8 CMPRF1 = 0x0 - Comparator reference 1 TRIG1 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O M1SCL = 0x4 - Serial I2C Master Clock output (IOM 1) M1SCK = 0x5 - Serial SPI Master Clock output (IOM 1) CT8 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE8 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS8 = 0x8 - Observation bus bit 8 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANOUT4 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010024 |
Controls the operation of GPIO pin 9.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN9
0x0 |
FIEN9
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL9
0x0 |
NCESRC9
0x0 |
PULLCFG9
0x0 |
SR9
0x0 |
DS9
0x0 |
OUTCFG9
0x0 |
IRPTEN9
0x0 |
RDZERO9
0x0 |
INPEN9
0x0 |
FNCSEL9
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN9 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN9 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL9 | RW | Polarity select for NCE for GPIO 9 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC9 | RW | IOMSTR/MSPI N Chip Select 9, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG9 | RW | Pullup/Pulldown configuration for GPIO 9 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR9 | RW | Configure the slew rate |
| 11:10 | DS9 | RW | Drive strength selection for GPIO 9 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG9 | RW | Pin IO mode selection for GPIO pin 9 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN9 | RW | Interrupt enable for GPIO 9 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO9 | RW | Return 0 for read data on GPIO 9 |
| 4 | INPEN9 | RW | Input enable for GPIO 9 |
| 3:0 | FNCSEL9 | RW | Function select for GPIO pin 9 CMPRF0 = 0x0 - Comparator reference 0 TRIG2 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O M1SDAWIR3 = 0x4 - Serial I2C Master Data I/O (I2C Mode) Serial SPI Master Data I/O (SPI 3 wire mode) (IOM 1) M1MOSI = 0x5 - Serial SPI Master MOSI output (IOM 1) CT9 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE9 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS9 = 0x8 - Observation bus bit 9 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANOUT5 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010028 |
Controls the operation of GPIO pin 10.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN10
0x0 |
FIEN10
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL10
0x0 |
NCESRC10
0x0 |
PULLCFG10
0x0 |
SR10
0x0 |
DS10
0x0 |
OUTCFG10
0x0 |
IRPTEN10
0x0 |
RDZERO10
0x0 |
INPEN10
0x0 |
FNCSEL10
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN10 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN10 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL10 | RW | Polarity select for NCE for GPIO 10 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC10 | RW | IOMSTR/MSPI N Chip Select 10, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG10 | RW | Pullup/Pulldown configuration for GPIO 10 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR10 | RW | Configure the slew rate |
| 11:10 | DS10 | RW | Drive strength selection for GPIO 10 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG10 | RW | Pin IO mode selection for GPIO pin 10 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN10 | RW | Interrupt enable for GPIO 10 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO10 | RW | Return 0 for read data on GPIO 10 |
| 4 | INPEN10 | RW | Input enable for GPIO 10 |
| 3:0 | FNCSEL10 | RW | Function select for GPIO pin 10 CMPIN0 = 0x0 - Voltage comparator input 0 TRIG3 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O M1MISO = 0x4 - Serial SPI MASTER MISO input (IOM 1) RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT10 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE10 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS10 = 0x8 - Observation bus bit 10 DISP_TE = 0x9 - Display TE input RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. OPCG_LOAD = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x4001002C |
Controls the operation of GPIO pin 11.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN11
0x0 |
FIEN11
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL11
0x0 |
NCESRC11
0x0 |
PULLCFG11
0x0 |
SR11
0x0 |
DS11
0x0 |
OUTCFG11
0x0 |
IRPTEN11
0x0 |
RDZERO11
0x0 |
INPEN11
0x0 |
FNCSEL11
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN11 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN11 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL11 | RW | Polarity select for NCE for GPIO 11 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC11 | RW | IOMSTR/MSPI N Chip Select 11, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG11 | RW | Pullup/Pulldown configuration for GPIO 11 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR11 | RW | Configure the slew rate |
| 11:10 | DS11 | RW | Drive strength selection for GPIO 11 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG11 | RW | Pin IO mode selection for GPIO pin 11 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN11 | RW | Interrupt enable for GPIO 11 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO11 | RW | Return 0 for read data on GPIO 11 |
| 4 | INPEN11 | RW | Input enable for GPIO 11 |
| 3:0 | FNCSEL11 | RW | Function select for GPIO pin 11 CMPIN1 = 0x0 - Voltage comparator input 1 TRIG0 = 0x1 - ADC trigger input I2S0_CLK = 0x2 - Bidirectional I2S Bit clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) UART3RX = 0x5 - UART receive input (UART 3) CT11 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE11 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS11 = 0x8 - Observation bus bit 11 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO FLB_TCLK = 0xC - Internal function (Flash Bist) FLLOAD_ADDR = 0xD - Internal function (Flash parallel load) MDA_TCK = 0xE - Internal function (MBIST) SCANIN0 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010030 |
Controls the operation of GPIO pin 12.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN12
0x0 |
FIEN12
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL12
0x0 |
NCESRC12
0x0 |
PULLCFG12
0x0 |
SR12
0x0 |
DS12
0x0 |
OUTCFG12
0x0 |
IRPTEN12
0x0 |
RDZERO12
0x0 |
INPEN12
0x0 |
FNCSEL12
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN12 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN12 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL12 | RW | Polarity select for NCE for GPIO 12 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC12 | RW | IOMSTR/MSPI N Chip Select 12, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG12 | RW | Pullup/Pulldown configuration for GPIO 12 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR12 | RW | Configure the slew rate |
| 11:10 | DS12 | RW | Drive strength selection for GPIO 12 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG12 | RW | Pin IO mode selection for GPIO pin 12 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN12 | RW | Interrupt enable for GPIO 12 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO12 | RW | Return 0 for read data on GPIO 12 |
| 4 | INPEN12 | RW | Input enable for GPIO 12 |
| 3:0 | FNCSEL12 | RW | Function select for GPIO pin 12 ADCSE7 = 0x0 - Analog to Digital Converter SE IN7 TRIG1 = 0x1 - ADC trigger input I2S0_DATA = 0x2 - Bidirectional I2S Data. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) UART1TX = 0x5 - UART transmit output (UART 1) CT12 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE12 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS12 = 0x8 - Observation bus bit 12 CMPRF2 = 0x9 - Comparator reference 2 I2S0_SDOUT = 0xA - I2S Data output (I2S Master/Slave 2) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANOUT3 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010034 |
Controls the operation of GPIO pin 13.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN13
0x0 |
FIEN13
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL13
0x0 |
NCESRC13
0x0 |
PULLCFG13
0x0 |
SR13
0x0 |
DS13
0x0 |
OUTCFG13
0x0 |
IRPTEN13
0x0 |
RDZERO13
0x0 |
INPEN13
0x0 |
FNCSEL13
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN13 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN13 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL13 | RW | Polarity select for NCE for GPIO 13 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC13 | RW | IOMSTR/MSPI N Chip Select 13, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG13 | RW | Pullup/Pulldown configuration for GPIO 13 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR13 | RW | Configure the slew rate |
| 11:10 | DS13 | RW | Drive strength selection for GPIO 13 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG13 | RW | Pin IO mode selection for GPIO pin 13 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN13 | RW | Interrupt enable for GPIO 13 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO13 | RW | Return 0 for read data on GPIO 13 |
| 4 | INPEN13 | RW | Input enable for GPIO 13 |
| 3:0 | FNCSEL13 | RW | Function select for GPIO pin 13 ADCSE6 = 0x0 - Analog to Digital Converter SE IN6 TRIG2 = 0x1 - ADC trigger input I2S0_WS = 0x2 - Bidirectional I2S L/R clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) UART3TX = 0x5 - UART transmit output (UART 3) CT13 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE13 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS13 = 0x8 - Observation bus bit 13 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO FLB_FCLK = 0xC - Internal function (Flash Bist) FLLOAD_DATA = 0xD - Internal function (Flash parallel load) MDA_TDI = 0xE - Internal function (MBIST) SCANOUT0 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010038 |
Controls the operation of GPIO pin 14.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN14
0x0 |
FIEN14
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL14
0x0 |
NCESRC14
0x0 |
PULLCFG14
0x0 |
SR14
0x0 |
DS14
0x0 |
OUTCFG14
0x0 |
IRPTEN14
0x0 |
RDZERO14
0x0 |
INPEN14
0x0 |
FNCSEL14
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN14 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN14 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL14 | RW | Polarity select for NCE for GPIO 14 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC14 | RW | IOMSTR/MSPI N Chip Select 14, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG14 | RW | Pullup/Pulldown configuration for GPIO 14 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR14 | RW | Configure the slew rate |
| 11:10 | DS14 | RW | Drive strength selection for GPIO 14 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG14 | RW | Pin IO mode selection for GPIO pin 14 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN14 | RW | Interrupt enable for GPIO 14 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO14 | RW | Return 0 for read data on GPIO 14 |
| 4 | INPEN14 | RW | Input enable for GPIO 14 |
| 3:0 | FNCSEL14 | RW | Function select for GPIO pin 14 ADCSE5 = 0x0 - Analog to Digital Converter SE IN5 TRIG3 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O MILLI_CLK = 0x4 - MILLI Clock UART1RX = 0x5 - UART receive input (UART 1) CT14 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE14 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS14 = 0x8 - Observation bus bit 14 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. I2S0_SDIN = 0xA - I2S Data input (I2S Master/Slave 2) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. FLLOAD_ADDR = 0xD - Internal function (Flash parallel load) MDA_TRSTN = 0xE - Internal function (MBIST) SCANOUT2 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x4001003C |
Controls the operation of GPIO pin 15.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN15
0x0 |
FIEN15
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL15
0x0 |
NCESRC15
0x0 |
PULLCFG15
0x0 |
SR15
0x0 |
DS15
0x0 |
OUTCFG15
0x0 |
IRPTEN15
0x0 |
RDZERO15
0x0 |
INPEN15
0x0 |
FNCSEL15
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN15 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN15 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL15 | RW | Polarity select for NCE for GPIO 15 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC15 | RW | IOMSTR/MSPI N Chip Select 15, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG15 | RW | Pullup/Pulldown configuration for GPIO 15 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR15 | RW | Configure the slew rate |
| 11:10 | DS15 | RW | Drive strength selection for GPIO 15 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG15 | RW | Pin IO mode selection for GPIO pin 15 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN15 | RW | Interrupt enable for GPIO 15 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO15 | RW | Return 0 for read data on GPIO 15 |
| 4 | INPEN15 | RW | Input enable for GPIO 15 |
| 3:0 | FNCSEL15 | RW | Function select for GPIO pin 15 ADCSE4 = 0x0 - Analog to Digital Converter SE IN4 TRIG0 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O MILLI_REC_DAT = 0x4 - MILLI Record Data UART3RX = 0x5 - UART receive input (UART 3) CT15 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE15 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS15 = 0x8 - Observation bus bit 15 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. REFCLK_EXT = 0xA - External Reference Clock FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. FLLOAD_DATA = 0xD - Internal function (Flash parallel load) RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANOUT1 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010040 |
Controls the operation of GPIO pin 16.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN16
0x0 |
FIEN16
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL16
0x0 |
NCESRC16
0x0 |
PULLCFG16
0x0 |
SR16
0x0 |
DS16
0x0 |
OUTCFG16
0x0 |
IRPTEN16
0x0 |
RDZERO16
0x0 |
INPEN16
0x0 |
FNCSEL16
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN16 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN16 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL16 | RW | Polarity select for NCE for GPIO 16 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC16 | RW | IOMSTR/MSPI N Chip Select 16, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG16 | RW | Pullup/Pulldown configuration for GPIO 16 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR16 | RW | Configure the slew rate |
| 11:10 | DS16 | RW | Drive strength selection for GPIO 16 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG16 | RW | Pin IO mode selection for GPIO pin 16 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN16 | RW | Interrupt enable for GPIO 16 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO16 | RW | Return 0 for read data on GPIO 16 |
| 4 | INPEN16 | RW | Input enable for GPIO 16 |
| 3:0 | FNCSEL16 | RW | Function select for GPIO pin 16 ADCSE3 = 0x0 - Analog to Digital Converter SE IN3 TRIG1 = 0x1 - ADC trigger input I2S1_CLK = 0x2 - Bidirectional I2S Bit clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O MILLI_PBDATA1 = 0x4 - MILLI Playback Data1 UART1RTS = 0x5 - UART Request to Send (RTS) (UART 1) CT16 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE16 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS0 = 0x8 - Observation bus bit 0 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. DFT_RET = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010044 |
Controls the operation of GPIO pin 17.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN17
0x0 |
FIEN17
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL17
0x0 |
NCESRC17
0x0 |
PULLCFG17
0x0 |
SR17
0x0 |
DS17
0x0 |
OUTCFG17
0x0 |
IRPTEN17
0x0 |
RDZERO17
0x0 |
INPEN17
0x0 |
FNCSEL17
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN17 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN17 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL17 | RW | Polarity select for NCE for GPIO 17 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC17 | RW | IOMSTR/MSPI N Chip Select 17, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG17 | RW | Pullup/Pulldown configuration for GPIO 17 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR17 | RW | Configure the slew rate |
| 11:10 | DS17 | RW | Drive strength selection for GPIO 17 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG17 | RW | Pin IO mode selection for GPIO pin 17 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN17 | RW | Interrupt enable for GPIO 17 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO17 | RW | Return 0 for read data on GPIO 17 |
| 4 | INPEN17 | RW | Input enable for GPIO 17 |
| 3:0 | FNCSEL17 | RW | Function select for GPIO pin 17 ADCSE2 = 0x0 - Analog to Digital Converter SE IN2 TRIG2 = 0x1 - ADC trigger input I2S1_DATA = 0x2 - Bidirectional I2S Data. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O MILLI_PBDATA2 = 0x4 - MILLI Playback Data2 UART3RTS = 0x5 - UART Request to Send (RTS) (UART 3) CT17 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE17 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS1 = 0x8 - Observation bus bit 1 I2S1_SDOUT = 0x9 - I2S Data output (I2S Master/Slave 2) RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. FLLOAD_STRB = 0xD - Internal function (Flash parallel load) MDA_TMS = 0xE - Internal function (MBIST) OPCG_CLK = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010048 |
Controls the operation of GPIO pin 18.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN18
0x0 |
FIEN18
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL18
0x0 |
NCESRC18
0x0 |
PULLCFG18
0x0 |
SR18
0x0 |
DS18
0x0 |
OUTCFG18
0x0 |
IRPTEN18
0x0 |
RDZERO18
0x0 |
INPEN18
0x0 |
FNCSEL18
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN18 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN18 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL18 | RW | Polarity select for NCE for GPIO 18 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC18 | RW | IOMSTR/MSPI N Chip Select 18, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG18 | RW | Pullup/Pulldown configuration for GPIO 18 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR18 | RW | Configure the slew rate |
| 11:10 | DS18 | RW | Drive strength selection for GPIO 18 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG18 | RW | Pin IO mode selection for GPIO pin 18 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN18 | RW | Interrupt enable for GPIO 18 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO18 | RW | Return 0 for read data on GPIO 18 |
| 4 | INPEN18 | RW | Input enable for GPIO 18 |
| 3:0 | FNCSEL18 | RW | Function select for GPIO pin 18 ADCSE1 = 0x0 - Analog to Digital Converter SE IN1 ANATEST2 = 0x1 - Ambiq Analog test I/O - Unbuffered I2S1_WS = 0x2 - Bidirectional I2S L/R clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART0CTS = 0x4 - UART Clear to Send (CTS) (UART 0) UART1CTS = 0x5 - UART Clear to Send (CTS) (UART 1) CT18 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE18 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS2 = 0x8 - Observation bus bit 2 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO FLB_TMS = 0xC - Internal function (Flash Bist) FLLOAD_DATA = 0xD - Internal function (Flash parallel load) MDA_HFRC_EXT = 0xE - Internal function (MBIST) SCANIN1 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x4001004C |
Controls the operation of GPIO pin 19.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN19
0x0 |
FIEN19
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL19
0x0 |
NCESRC19
0x0 |
PULLCFG19
0x0 |
SR19
0x0 |
DS19
0x0 |
OUTCFG19
0x0 |
IRPTEN19
0x0 |
RDZERO19
0x0 |
INPEN19
0x0 |
FNCSEL19
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN19 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN19 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL19 | RW | Polarity select for NCE for GPIO 19 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC19 | RW | IOMSTR/MSPI N Chip Select 19, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG19 | RW | Pullup/Pulldown configuration for GPIO 19 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR19 | RW | Configure the slew rate |
| 11:10 | DS19 | RW | Drive strength selection for GPIO 19 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG19 | RW | Pin IO mode selection for GPIO pin 19 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN19 | RW | Interrupt enable for GPIO 19 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO19 | RW | Return 0 for read data on GPIO 19 |
| 4 | INPEN19 | RW | Input enable for GPIO 19 |
| 3:0 | FNCSEL19 | RW | Function select for GPIO pin 19 ADCSE0 = 0x0 - Analog to Digital Converter SE IN0 ANATEST1 = 0x1 - Ambiq Analog test I/O - Buffered RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART2CTS = 0x4 - UART Clear to Send (CTS) (UART 2) UART3CTS = 0x5 - UART Clear to Send (CTS) (UART 3) CT19 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE19 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS3 = 0x8 - Observation bus bit 3 I2S1_SDIN = 0x9 - I2S Data input (I2S Master/Slave 2) RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO FLB_TRSTN = 0xC - Internal function (Flash Bist) FLLOAD_ADDR = 0xD - Internal function (Flash parallel load) RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANIN2 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010050 |
Controls the operation of GPIO pin 20.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN20
0x0 |
FIEN20
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL20
0x0 |
NCESRC20
0x0 |
PULLCFG20
0x0 |
SR20
0x0 |
DS20
0x0 |
OUTCFG20
0x0 |
IRPTEN20
0x0 |
RDZERO20
0x0 |
INPEN20
0x0 |
FNCSEL20
0x0 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN20 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN20 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL20 | RW | Polarity select for NCE for GPIO 20 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC20 | RW | IOMSTR/MSPI N Chip Select 20, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG20 | RW | Pullup/Pulldown configuration for GPIO 20 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR20 | RW | Configure the slew rate |
| 11:10 | DS20 | RW | Drive strength selection for GPIO 20 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG20 | RW | Pin IO mode selection for GPIO pin 20 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN20 | RW | Interrupt enable for GPIO 20 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO20 | RW | Return 0 for read data on GPIO 20 |
| 4 | INPEN20 | RW | Input enable for GPIO 20 |
| 3:0 | FNCSEL20 | RW | Function select for GPIO pin 20 SWDCK = 0x0 - Serial Wire Debug clock input TRIG1 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) UART1TX = 0x5 - UART transmit output (UART 1) CT20 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE20 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS4 = 0x8 - Observation bus bit 4 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANCLK = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010054 |
Controls the operation of GPIO pin 21.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN21
0x0 |
FIEN21
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL21
0x0 |
NCESRC21
0x0 |
PULLCFG21
0x0 |
SR21
0x0 |
DS21
0x0 |
OUTCFG21
0x0 |
IRPTEN21
0x0 |
RDZERO21
0x0 |
INPEN21
0x0 |
FNCSEL21
0x0 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN21 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN21 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL21 | RW | Polarity select for NCE for GPIO 21 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC21 | RW | IOMSTR/MSPI N Chip Select 21, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG21 | RW | Pullup/Pulldown configuration for GPIO 21 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR21 | RW | Configure the slew rate |
| 11:10 | DS21 | RW | Drive strength selection for GPIO 21 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG21 | RW | Pin IO mode selection for GPIO pin 21 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN21 | RW | Interrupt enable for GPIO 21 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO21 | RW | Return 0 for read data on GPIO 21 |
| 4 | INPEN21 | RW | Input enable for GPIO 21 |
| 3:0 | FNCSEL21 | RW | Function select for GPIO pin 21 SWDIO = 0x0 - Serial Wire Debug data input/output TRIG2 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) UART3TX = 0x5 - UART transmit output (UART 3) CT21 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE21 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS5 = 0x8 - Observation bus bit 5 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANSHFT = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010058 |
Controls the operation of GPIO pin 22.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN22
0x0 |
FIEN22
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL22
0x0 |
NCESRC22
0x0 |
PULLCFG22
0x0 |
SR22
0x0 |
DS22
0x0 |
OUTCFG22
0x0 |
IRPTEN22
0x0 |
RDZERO22
0x0 |
INPEN22
0x0 |
FNCSEL22
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN22 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN22 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL22 | RW | Polarity select for NCE for GPIO 22 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC22 | RW | IOMSTR/MSPI N Chip Select 22, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG22 | RW | Pullup/Pulldown configuration for GPIO 22 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR22 | RW | Configure the slew rate |
| 11:10 | DS22 | RW | Drive strength selection for GPIO 22 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG22 | RW | Pin IO mode selection for GPIO pin 22 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN22 | RW | Interrupt enable for GPIO 22 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO22 | RW | Return 0 for read data on GPIO 22 |
| 4 | INPEN22 | RW | Input enable for GPIO 22 |
| 3:0 | FNCSEL22 | RW | Function select for GPIO pin 22 M7SCL = 0x0 - Serial I2C Master Clock output (IOM 7) M7SCK = 0x1 - Serial SPI Master Clock output (IOM 7) SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) UART1RX = 0x5 - UART receive input (UART 1) CT22 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE22 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS6 = 0x8 - Observation bus bit 6 VCMPO = 0x9 - Output of the voltage comparator signal I3CM1_SCL = 0xA - Serial I3C Master Clock output (IOM 1) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANIN3 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x4001005C |
Controls the operation of GPIO pin 23.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN23
0x0 |
FIEN23
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL23
0x0 |
NCESRC23
0x0 |
PULLCFG23
0x0 |
SR23
0x0 |
DS23
0x0 |
OUTCFG23
0x0 |
IRPTEN23
0x0 |
RDZERO23
0x0 |
INPEN23
0x0 |
FNCSEL23
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN23 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN23 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL23 | RW | Polarity select for NCE for GPIO 23 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC23 | RW | IOMSTR/MSPI N Chip Select 23, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG23 | RW | Pullup/Pulldown configuration for GPIO 23 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR23 | RW | Configure the slew rate |
| 11:10 | DS23 | RW | Drive strength selection for GPIO 23 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG23 | RW | Pin IO mode selection for GPIO pin 23 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN23 | RW | Interrupt enable for GPIO 23 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO23 | RW | Return 0 for read data on GPIO 23 |
| 4 | INPEN23 | RW | Input enable for GPIO 23 |
| 3:0 | FNCSEL23 | RW | Function select for GPIO pin 23 M7SDAWIR3 = 0x0 - Serial I2C Master Data I/O (I2C Mode) Serial SPI Master Data I/O (SPI 3 wire mode) (IOM 7) M7MOSI = 0x1 - Serial SPI Master MOSI output (IOM 7) SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) UART3RX = 0x5 - UART receive input (UART 3) CT23 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE23 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS7 = 0x8 - Observation bus bit 7 VCMPO = 0x9 - Output of the voltage comparator signal I3CM1_SDA = 0xA - Serial I3C Master Data I/O (IOM 1) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANOUT6 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010060 |
Controls the operation of GPIO pin 24.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN24
0x0 |
FIEN24
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL24
0x0 |
NCESRC24
0x0 |
PULLCFG24
0x0 |
SR24
0x0 |
DS24
0x0 |
OUTCFG24
0x0 |
IRPTEN24
0x0 |
RDZERO24
0x0 |
INPEN24
0x0 |
FNCSEL24
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN24 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN24 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL24 | RW | Polarity select for NCE for GPIO 24 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC24 | RW | IOMSTR/MSPI N Chip Select 24, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG24 | RW | Pullup/Pulldown configuration for GPIO 24 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR24 | RW | Configure the slew rate |
| 11:10 | DS24 | RW | Drive strength selection for GPIO 24 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG24 | RW | Pin IO mode selection for GPIO pin 24 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN24 | RW | Interrupt enable for GPIO 24 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO24 | RW | Return 0 for read data on GPIO 24 |
| 4 | INPEN24 | RW | Input enable for GPIO 24 |
| 3:0 | FNCSEL24 | RW | Function select for GPIO pin 24 M7MISO = 0x0 - Serial SPI MASTER MISO input (IOM 7) TRIG3 = 0x1 - ADC trigger input SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART0RTS = 0x4 - UART Request to Send (RTS) (UART 0) UART1RTS = 0x5 - UART Request to Send (RTS) (UART 1) CT24 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE24 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS8 = 0x8 - Observation bus bit 8 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANOUT7 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010064 |
Controls the operation of GPIO pin 25.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN25
0x0 |
FIEN25
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL25
0x0 |
NCESRC25
0x0 |
PULLCFG25
0x0 |
SR25
0x0 |
DS25
0x0 |
OUTCFG25
0x0 |
IRPTEN25
0x0 |
RDZERO25
0x0 |
INPEN25
0x0 |
FNCSEL25
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN25 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN25 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL25 | RW | Polarity select for NCE for GPIO 25 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC25 | RW | IOMSTR/MSPI N Chip Select 25, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG25 | RW | Pullup/Pulldown configuration for GPIO 25 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR25 | RW | Configure the slew rate |
| 11:10 | DS25 | RW | Drive strength selection for GPIO 25 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG25 | RW | Pin IO mode selection for GPIO pin 25 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN25 | RW | Interrupt enable for GPIO 25 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO25 | RW | Return 0 for read data on GPIO 25 |
| 4 | INPEN25 | RW | Input enable for GPIO 25 |
| 3:0 | FNCSEL25 | RW | Function select for GPIO pin 25 M2SCL = 0x0 - Serial I2C Master Clock output (IOM 2) M2SCK = 0x1 - Serial SPI Master Clock output (IOM 2) RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O LFRC_EXT = 0x4 - External LFRC Clock DSP_TMS = 0x5 - JTAG tms input CT25 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE25 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS9 = 0x8 - Observation bus bit 9 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANIN8 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010068 |
Controls the operation of GPIO pin 26.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN26
0x0 |
FIEN26
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL26
0x0 |
NCESRC26
0x0 |
PULLCFG26
0x0 |
SR26
0x0 |
DS26
0x0 |
OUTCFG26
0x0 |
IRPTEN26
0x0 |
RDZERO26
0x0 |
INPEN26
0x0 |
FNCSEL26
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN26 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN26 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL26 | RW | Polarity select for NCE for GPIO 26 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC26 | RW | IOMSTR/MSPI N Chip Select 26, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG26 | RW | Pullup/Pulldown configuration for GPIO 26 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR26 | RW | Configure the slew rate |
| 11:10 | DS26 | RW | Drive strength selection for GPIO 26 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG26 | RW | Pin IO mode selection for GPIO pin 26 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN26 | RW | Interrupt enable for GPIO 26 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO26 | RW | Return 0 for read data on GPIO 26 |
| 4 | INPEN26 | RW | Input enable for GPIO 26 |
| 3:0 | FNCSEL26 | RW | Function select for GPIO pin 26 M2SDAWIR3 = 0x0 - Serial I2C Master Data I/O (I2C Mode) Serial SPI Master Data I/O (SPI 3 wire mode) (IOM 2) M2MOSI = 0x1 - Serial SPI Master MOSI output (IOM 2) RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O HFRC_EXT = 0x4 - External HFRC Clock RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT26 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE26 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS10 = 0x8 - Observation bus bit 10 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANIN9 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x4001006C |
Controls the operation of GPIO pin 27.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN27
0x0 |
FIEN27
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL27
0x0 |
NCESRC27
0x0 |
PULLCFG27
0x0 |
SR27
0x0 |
DS27
0x0 |
OUTCFG27
0x0 |
IRPTEN27
0x0 |
RDZERO27
0x0 |
INPEN27
0x0 |
FNCSEL27
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN27 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN27 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL27 | RW | Polarity select for NCE for GPIO 27 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC27 | RW | IOMSTR/MSPI N Chip Select 27, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG27 | RW | Pullup/Pulldown configuration for GPIO 27 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR27 | RW | Configure the slew rate |
| 11:10 | DS27 | RW | Drive strength selection for GPIO 27 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG27 | RW | Pin IO mode selection for GPIO pin 27 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN27 | RW | Interrupt enable for GPIO 27 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO27 | RW | Return 0 for read data on GPIO 27 |
| 4 | INPEN27 | RW | Input enable for GPIO 27 |
| 3:0 | FNCSEL27 | RW | Function select for GPIO pin 27 M2MISO = 0x0 - Serial SPI MASTER MISO input (IOM 2) TRIG0 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O XT_EXT = 0x4 - External XT Clock DSP_TCK = 0x5 - JTAG tck clock interface CT27 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE27 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS11 = 0x8 - Observation bus bit 11 I2S0_SDIN = 0x9 - I2S Data input (I2S Master/Slave 2) RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANIN10 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010070 |
Controls the operation of GPIO pin 28.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN28
0x0 |
FIEN28
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL28
0x0 |
NCESRC28
0x0 |
PULLCFG28
0x0 |
SR28
0x0 |
DS28
0x0 |
OUTCFG28
0x0 |
IRPTEN28
0x0 |
RDZERO28
0x0 |
INPEN28
0x0 |
FNCSEL28
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN28 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN28 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL28 | RW | Polarity select for NCE for GPIO 28 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC28 | RW | IOMSTR/MSPI N Chip Select 28, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG28 | RW | Pullup/Pulldown configuration for GPIO 28 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR28 | RW | Configure the slew rate |
| 11:10 | DS28 | RW | Drive strength selection for GPIO 28 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG28 | RW | Pin IO mode selection for GPIO pin 28 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN28 | RW | Interrupt enable for GPIO 28 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO28 | RW | Return 0 for read data on GPIO 28 |
| 4 | INPEN28 | RW | Input enable for GPIO 28 |
| 3:0 | FNCSEL28 | RW | Function select for GPIO pin 28 SWO = 0x0 - Serial Wire Output VCMPO = 0x1 - Output of the voltage comparator signal I2S0_CLK = 0x2 - Bidirectional I2S Bit clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART2CTS = 0x4 - UART Clear to Send (CTS) (UART 2) DSP_TDO = 0x5 - JTAG tdo output CT28 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE28 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS12 = 0x8 - Observation bus bit 12 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. CME = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010074 |
Controls the operation of GPIO pin 29.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN29
0x0 |
FIEN29
0x0 |
RSVD25
0x0 |
RESERVED23
0x0 |
NCEPOL29
0x0 |
NCESRC29
0x0 |
PULLCFG29
0x0 |
SR29
0x0 |
DS29
0x0 |
OUTCFG29
0x0 |
IRPTEN29
0x0 |
RDZERO29
0x0 |
INPEN29
0x0 |
FNCSEL29
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN29 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN29 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RSVD25 | RW | RESERVED - this field should not be modified |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL29 | RW | Polarity select for NCE for GPIO 29 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC29 | RW | IOMSTR/MSPI N Chip Select 29, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG29 | RW | Pullup/Pulldown configuration for GPIO 29 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR29 | RW | Configure the slew rate |
| 11:10 | DS29 | RW | Drive strength selection for GPIO 29 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG29 | RW | Pin IO mode selection for GPIO pin 29 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN29 | RW | Interrupt enable for GPIO 29 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO29 | RW | Return 0 for read data on GPIO 29 |
| 4 | INPEN29 | RW | Input enable for GPIO 29 |
| 3:0 | FNCSEL29 | RW | Function select for GPIO pin 29 TRIG0 = 0x0 - ADC trigger input VCMPO = 0x1 - Output of the voltage comparator signal I2S0_DATA = 0x2 - Bidirectional I2S Data. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART1CTS = 0x4 - UART Clear to Send (CTS) (UART 1) DSP_TRSTN = 0x5 - JTAG TRSTN input CT29 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE29 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS13 = 0x8 - Observation bus bit 13 I2S0_SDOUT = 0x9 - I2S Data output (I2S Master/Slave 2) RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. CMLE = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010078 |
Controls the operation of GPIO pin 30.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN30
0x0 |
FIEN30
0x0 |
RSVD25
0x0 |
RESERVED23
0x0 |
NCEPOL30
0x0 |
NCESRC30
0x0 |
PULLCFG30
0x0 |
SR30
0x0 |
DS30
0x0 |
OUTCFG30
0x0 |
IRPTEN30
0x0 |
RDZERO30
0x0 |
INPEN30
0x0 |
FNCSEL30
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN30 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN30 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RSVD25 | RW | RESERVED - this field should not be modified |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL30 | RW | Polarity select for NCE for GPIO 30 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC30 | RW | IOMSTR/MSPI N Chip Select 30, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG30 | RW | Pullup/Pulldown configuration for GPIO 30 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR30 | RW | Configure the slew rate |
| 11:10 | DS30 | RW | Drive strength selection for GPIO 30 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG30 | RW | Pin IO mode selection for GPIO pin 30 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN30 | RW | Interrupt enable for GPIO 30 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO30 | RW | Return 0 for read data on GPIO 30 |
| 4 | INPEN30 | RW | Input enable for GPIO 30 |
| 3:0 | FNCSEL30 | RW | Function select for GPIO pin 30 TRIG1 = 0x0 - ADC trigger input VCMPO = 0x1 - Output of the voltage comparator signal I2S0_WS = 0x2 - Bidirectional I2S L/R clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) DSP_TDI = 0x5 - JTAG tdi input CT30 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE30 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS14 = 0x8 - Observation bus bit 14 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANOUT8 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x4001007C |
Controls the operation of GPIO pin 31.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN31
0x0 |
FIEN31
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL31
0x0 |
NCESRC31
0x0 |
PULLCFG31
0x0 |
SR31
0x0 |
DS31
0x0 |
OUTCFG31
0x0 |
IRPTEN31
0x0 |
RDZERO31
0x0 |
INPEN31
0x0 |
FNCSEL31
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN31 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN31 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL31 | RW | Polarity select for NCE for GPIO 31 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC31 | RW | IOMSTR/MSPI N Chip Select 31, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG31 | RW | Pullup/Pulldown configuration for GPIO 31 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR31 | RW | Configure the slew rate |
| 11:10 | DS31 | RW | Drive strength selection for GPIO 31 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG31 | RW | Pin IO mode selection for GPIO pin 31 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN31 | RW | Interrupt enable for GPIO 31 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO31 | RW | Return 0 for read data on GPIO 31 |
| 4 | INPEN31 | RW | Input enable for GPIO 31 |
| 3:0 | FNCSEL31 | RW | Function select for GPIO pin 31 M3SCL = 0x0 - Serial I2C Master Clock output (IOM 3) M3SCK = 0x1 - Serial SPI Master Clock output (IOM 3) RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT31 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE31 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS15 = 0x8 - Observation bus bit 15 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. SCANOUT9 = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010080 |
Controls the operation of GPIO pin 32.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN32
0x0 |
FIEN32
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL32
0x0 |
NCESRC32
0x0 |
PULLCFG32
0x0 |
SR32
0x0 |
DS32
0x0 |
OUTCFG32
0x0 |
IRPTEN32
0x0 |
RDZERO32
0x0 |
INPEN32
0x0 |
FNCSEL32
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN32 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN32 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL32 | RW | Polarity select for NCE for GPIO 32 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC32 | RW | IOMSTR/MSPI N Chip Select 32, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG32 | RW | Pullup/Pulldown configuration for GPIO 32 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR32 | RW | Configure the slew rate |
| 11:10 | DS32 | RW | Drive strength selection for GPIO 32 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG32 | RW | Pin IO mode selection for GPIO pin 32 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN32 | RW | Interrupt enable for GPIO 32 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO32 | RW | Return 0 for read data on GPIO 32 |
| 4 | INPEN32 | RW | Input enable for GPIO 32 |
| 3:0 | FNCSEL32 | RW | Function select for GPIO pin 32 M3SDAWIR3 = 0x0 - Serial I2C Master Data I/O (I2C Mode) Serial SPI Master Data I/O (SPI 3 wire mode) (IOM 3) M3MOSI = 0x1 - Serial SPI Master MOSI output (IOM 3) RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT32 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE32 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS0 = 0x8 - Observation bus bit 0 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. LPG_ENABLE = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010084 |
Controls the operation of GPIO pin 33.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN33
0x0 |
FIEN33
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL33
0x0 |
NCESRC33
0x0 |
PULLCFG33
0x0 |
SR33
0x0 |
DS33
0x0 |
OUTCFG33
0x0 |
IRPTEN33
0x0 |
RDZERO33
0x0 |
INPEN33
0x0 |
FNCSEL33
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN33 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN33 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL33 | RW | Polarity select for NCE for GPIO 33 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC33 | RW | IOMSTR/MSPI N Chip Select 33, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG33 | RW | Pullup/Pulldown configuration for GPIO 33 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR33 | RW | Configure the slew rate |
| 11:10 | DS33 | RW | Drive strength selection for GPIO 33 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG33 | RW | Pin IO mode selection for GPIO pin 33 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN33 | RW | Interrupt enable for GPIO 33 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO33 | RW | Return 0 for read data on GPIO 33 |
| 4 | INPEN33 | RW | Input enable for GPIO 33 |
| 3:0 | FNCSEL33 | RW | Function select for GPIO pin 33 M3MISO = 0x0 - Serial SPI MASTER MISO input (IOM 3) CLKOUT = 0x1 - Oscillator output clock RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT33 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE33 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS1 = 0x8 - Observation bus bit 1 DISP_TE = 0x9 - Display TE input RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. LPG_LOAD = 0xF - Internal function (SCAN) |
| Instance 0 Address: | 0x40010088 |
Controls the operation of GPIO pin 34.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN34
0x0 |
FIEN34
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL34
0x0 |
NCESRC34
0x0 |
PULLCFG34
0x0 |
SR34
0x0 |
DS34
0x0 |
OUTCFG34
0x0 |
IRPTEN34
0x0 |
RDZERO34
0x0 |
INPEN34
0x0 |
FNCSEL34
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN34 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN34 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL34 | RW | Polarity select for NCE for GPIO 34 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC34 | RW | IOMSTR/MSPI N Chip Select 34, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG34 | RW | Pullup/Pulldown configuration for GPIO 34 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR34 | RW | Configure the slew rate |
| 11:10 | DS34 | RW | Drive strength selection for GPIO 34 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG34 | RW | Pin IO mode selection for GPIO pin 34 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN34 | RW | Interrupt enable for GPIO 34 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO34 | RW | Return 0 for read data on GPIO 34 |
| 4 | INPEN34 | RW | Input enable for GPIO 34 |
| 3:0 | FNCSEL34 | RW | Function select for GPIO pin 34 M4SCL = 0x0 - Serial I2C Master Clock output (IOM 4) M4SCK = 0x1 - Serial SPI Master Clock output (IOM 4) SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT34 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE34 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS2 = 0x8 - Observation bus bit 2 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001008C |
Controls the operation of GPIO pin 35.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN35
0x0 |
FIEN35
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL35
0x0 |
NCESRC35
0x0 |
PULLCFG35
0x0 |
SR35
0x0 |
DS35
0x0 |
OUTCFG35
0x0 |
IRPTEN35
0x0 |
RDZERO35
0x0 |
INPEN35
0x0 |
FNCSEL35
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN35 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN35 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL35 | RW | Polarity select for NCE for GPIO 35 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC35 | RW | IOMSTR/MSPI N Chip Select 35, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG35 | RW | Pullup/Pulldown configuration for GPIO 35 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR35 | RW | Configure the slew rate |
| 11:10 | DS35 | RW | Drive strength selection for GPIO 35 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG35 | RW | Pin IO mode selection for GPIO pin 35 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN35 | RW | Interrupt enable for GPIO 35 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO35 | RW | Return 0 for read data on GPIO 35 |
| 4 | INPEN35 | RW | Input enable for GPIO 35 |
| 3:0 | FNCSEL35 | RW | Function select for GPIO pin 35 M4SDAWIR3 = 0x0 - Serial I2C Master Data I/O (I2C Mode) Serial SPI Master Data I/O (SPI 3 wire mode) (IOM 4) M4MOSI = 0x1 - Serial SPI Master MOSI output (IOM 4) SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) UART3TX = 0x5 - UART transmit output (UART 3) CT35 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE35 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS3 = 0x8 - Observation bus bit 3 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010090 |
Controls the operation of GPIO pin 36.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN36
0x0 |
FIEN36
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL36
0x0 |
NCESRC36
0x0 |
PULLCFG36
0x0 |
SR36
0x0 |
DS36
0x0 |
OUTCFG36
0x0 |
IRPTEN36
0x0 |
RDZERO36
0x0 |
INPEN36
0x0 |
FNCSEL36
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN36 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN36 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL36 | RW | Polarity select for NCE for GPIO 36 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC36 | RW | IOMSTR/MSPI N Chip Select 36, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG36 | RW | Pullup/Pulldown configuration for GPIO 36 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR36 | RW | Configure the slew rate |
| 11:10 | DS36 | RW | Drive strength selection for GPIO 36 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG36 | RW | Pin IO mode selection for GPIO pin 36 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN36 | RW | Interrupt enable for GPIO 36 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO36 | RW | Return 0 for read data on GPIO 36 |
| 4 | INPEN36 | RW | Input enable for GPIO 36 |
| 3:0 | FNCSEL36 | RW | Function select for GPIO pin 36 M4MISO = 0x0 - Serial SPI MASTER MISO input (IOM 4) TRIG0 = 0x1 - ADC trigger input SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) UART1RX = 0x5 - UART receive input (UART 1) CT36 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE36 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS4 = 0x8 - Observation bus bit 4 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010094 |
Controls the operation of GPIO pin 37.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN37
0x0 |
FIEN37
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL37
0x0 |
NCESRC37
0x0 |
PULLCFG37
0x0 |
SR37
0x0 |
DS37
0x0 |
OUTCFG37
0x0 |
IRPTEN37
0x0 |
RDZERO37
0x0 |
INPEN37
0x0 |
FNCSEL37
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN37 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN37 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL37 | RW | Polarity select for NCE for GPIO 37 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC37 | RW | IOMSTR/MSPI N Chip Select 37, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG37 | RW | Pullup/Pulldown configuration for GPIO 37 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR37 | RW | Configure the slew rate |
| 11:10 | DS37 | RW | Drive strength selection for GPIO 37 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG37 | RW | Pin IO mode selection for GPIO pin 37 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN37 | RW | Interrupt enable for GPIO 37 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO37 | RW | Return 0 for read data on GPIO 37 |
| 4 | INPEN37 | RW | Input enable for GPIO 37 |
| 3:0 | FNCSEL37 | RW | Function select for GPIO pin 37 MSPI1_0 = 0x0 - MSPI Master 1 Interface Signal TRIG1 = 0x1 - ADC trigger input 32KHzXT = 0x2 - 32kHZ from analog GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) DISP_D15 = 0x5 - Display Data 15 CT37 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE37 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS5 = 0x8 - Observation bus bit 5 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010098 |
Controls the operation of GPIO pin 38.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN38
0x0 |
FIEN38
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL38
0x0 |
NCESRC38
0x0 |
PULLCFG38
0x0 |
SR38
0x0 |
DS38
0x0 |
OUTCFG38
0x0 |
IRPTEN38
0x0 |
RDZERO38
0x0 |
INPEN38
0x0 |
FNCSEL38
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN38 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN38 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL38 | RW | Polarity select for NCE for GPIO 38 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC38 | RW | IOMSTR/MSPI N Chip Select 38, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG38 | RW | Pullup/Pulldown configuration for GPIO 38 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR38 | RW | Configure the slew rate |
| 11:10 | DS38 | RW | Drive strength selection for GPIO 38 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG38 | RW | Pin IO mode selection for GPIO pin 38 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN38 | RW | Interrupt enable for GPIO 38 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO38 | RW | Return 0 for read data on GPIO 38 |
| 4 | INPEN38 | RW | Input enable for GPIO 38 |
| 3:0 | FNCSEL38 | RW | Function select for GPIO pin 38 MSPI1_1 = 0x0 - MSPI Master 1 Interface Signal TRIG2 = 0x1 - ADC trigger input SWTRACECLK = 0x2 - Serial Wire Debug Trace Clock GPIO = 0x3 - General purpose I/O UART0RTS = 0x4 - UART Request to Send (RTS) (UART 0) DISP_D16 = 0x5 - Display Data 16 CT38 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE38 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS6 = 0x8 - Observation bus bit 6 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001009C |
Controls the operation of GPIO pin 39.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN39
0x0 |
FIEN39
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL39
0x0 |
NCESRC39
0x0 |
PULLCFG39
0x0 |
SR39
0x0 |
DS39
0x0 |
OUTCFG39
0x0 |
IRPTEN39
0x0 |
RDZERO39
0x0 |
INPEN39
0x0 |
FNCSEL39
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN39 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN39 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL39 | RW | Polarity select for NCE for GPIO 39 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC39 | RW | IOMSTR/MSPI N Chip Select 39, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG39 | RW | Pullup/Pulldown configuration for GPIO 39 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR39 | RW | Configure the slew rate |
| 11:10 | DS39 | RW | Drive strength selection for GPIO 39 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG39 | RW | Pin IO mode selection for GPIO pin 39 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN39 | RW | Interrupt enable for GPIO 39 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO39 | RW | Return 0 for read data on GPIO 39 |
| 4 | INPEN39 | RW | Input enable for GPIO 39 |
| 3:0 | FNCSEL39 | RW | Function select for GPIO pin 39 MSPI1_2 = 0x0 - MSPI Master 1 Interface Signal TRIG3 = 0x1 - ADC trigger input SWTRACE0 = 0x2 - Serial Wire Debug Trace Output 0 GPIO = 0x3 - General purpose I/O UART2RTS = 0x4 - UART Request to Send (RTS) (UART 2) DISP_D17 = 0x5 - Display Data 17 CT39 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE39 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS7 = 0x8 - Observation bus bit 7 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100A0 |
Controls the operation of GPIO pin 40.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN40
0x0 |
FIEN40
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL40
0x0 |
NCESRC40
0x0 |
PULLCFG40
0x0 |
SR40
0x0 |
DS40
0x0 |
OUTCFG40
0x0 |
IRPTEN40
0x0 |
RDZERO40
0x0 |
INPEN40
0x0 |
FNCSEL40
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN40 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN40 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL40 | RW | Polarity select for NCE for GPIO 40 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC40 | RW | IOMSTR/MSPI N Chip Select 40, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG40 | RW | Pullup/Pulldown configuration for GPIO 40 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR40 | RW | Configure the slew rate |
| 11:10 | DS40 | RW | Drive strength selection for GPIO 40 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG40 | RW | Pin IO mode selection for GPIO pin 40 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN40 | RW | Interrupt enable for GPIO 40 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO40 | RW | Return 0 for read data on GPIO 40 |
| 4 | INPEN40 | RW | Input enable for GPIO 40 |
| 3:0 | FNCSEL40 | RW | Function select for GPIO pin 40 MSPI1_3 = 0x0 - MSPI Master 1 Interface Signal TRIG1 = 0x1 - ADC trigger input SWTRACE1 = 0x2 - Serial Wire Debug Trace Output 1 GPIO = 0x3 - General purpose I/O UART0CTS = 0x4 - UART Clear to Send (CTS) (UART 0) DISP_D18 = 0x5 - Display Data 18 CT40 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE40 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS8 = 0x8 - Observation bus bit 8 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100A4 |
Controls the operation of GPIO pin 41.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN41
0x0 |
FIEN41
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL41
0x0 |
NCESRC41
0x0 |
PULLCFG41
0x0 |
SR41
0x0 |
DS41
0x0 |
OUTCFG41
0x0 |
IRPTEN41
0x0 |
RDZERO41
0x0 |
INPEN41
0x0 |
FNCSEL41
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN41 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN41 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL41 | RW | Polarity select for NCE for GPIO 41 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC41 | RW | IOMSTR/MSPI N Chip Select 41, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG41 | RW | Pullup/Pulldown configuration for GPIO 41 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR41 | RW | Configure the slew rate |
| 11:10 | DS41 | RW | Drive strength selection for GPIO 41 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG41 | RW | Pin IO mode selection for GPIO pin 41 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN41 | RW | Interrupt enable for GPIO 41 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO41 | RW | Return 0 for read data on GPIO 41 |
| 4 | INPEN41 | RW | Input enable for GPIO 41 |
| 3:0 | FNCSEL41 | RW | Function select for GPIO pin 41 MSPI1_4 = 0x0 - MSPI Master 1 Interface Signal TRIG0 = 0x1 - ADC trigger input SWTRACE2 = 0x2 - Serial Wire Debug Trace Output 2 GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) DISP_D19 = 0x5 - Display Data 19 CT41 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE41 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS9 = 0x8 - Observation bus bit 9 SWO = 0x9 - Serial Wire Output RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100A8 |
Controls the operation of GPIO pin 42.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN42
0x0 |
FIEN42
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL42
0x0 |
NCESRC42
0x0 |
PULLCFG42
0x0 |
SR42
0x0 |
DS42
0x0 |
OUTCFG42
0x0 |
IRPTEN42
0x0 |
RDZERO42
0x0 |
INPEN42
0x0 |
FNCSEL42
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN42 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN42 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL42 | RW | Polarity select for NCE for GPIO 42 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC42 | RW | IOMSTR/MSPI N Chip Select 42, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG42 | RW | Pullup/Pulldown configuration for GPIO 42 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR42 | RW | Configure the slew rate |
| 11:10 | DS42 | RW | Drive strength selection for GPIO 42 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG42 | RW | Pin IO mode selection for GPIO pin 42 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN42 | RW | Interrupt enable for GPIO 42 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO42 | RW | Return 0 for read data on GPIO 42 |
| 4 | INPEN42 | RW | Input enable for GPIO 42 |
| 3:0 | FNCSEL42 | RW | Function select for GPIO pin 42 MSPI1_5 = 0x0 - MSPI Master 1 Interface Signal TRIG2 = 0x1 - ADC trigger input SWTRACE3 = 0x2 - Serial Wire Debug Trace Output 3 GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) DISP_D20 = 0x5 - Display Data 20 CT42 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE42 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS10 = 0x8 - Observation bus bit 10 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100AC |
Controls the operation of GPIO pin 43.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN43
0x0 |
FIEN43
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL43
0x0 |
NCESRC43
0x0 |
PULLCFG43
0x0 |
SR43
0x0 |
DS43
0x0 |
OUTCFG43
0x0 |
IRPTEN43
0x0 |
RDZERO43
0x0 |
INPEN43
0x0 |
FNCSEL43
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN43 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN43 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL43 | RW | Polarity select for NCE for GPIO 43 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC43 | RW | IOMSTR/MSPI N Chip Select 43, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG43 | RW | Pullup/Pulldown configuration for GPIO 43 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR43 | RW | Configure the slew rate |
| 11:10 | DS43 | RW | Drive strength selection for GPIO 43 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG43 | RW | Pin IO mode selection for GPIO pin 43 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN43 | RW | Interrupt enable for GPIO 43 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO43 | RW | Return 0 for read data on GPIO 43 |
| 4 | INPEN43 | RW | Input enable for GPIO 43 |
| 3:0 | FNCSEL43 | RW | Function select for GPIO pin 43 MSPI1_6 = 0x0 - MSPI Master 1 Interface Signal TRIG3 = 0x1 - ADC trigger input SWTRACECTL = 0x2 - Serial Wire Debug Trace Control GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) DISP_D21 = 0x5 - Display Data 21 CT43 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE43 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS11 = 0x8 - Observation bus bit 11 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100B0 |
Controls the operation of GPIO pin 44.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN44
0x0 |
FIEN44
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL44
0x0 |
NCESRC44
0x0 |
PULLCFG44
0x0 |
SR44
0x0 |
DS44
0x0 |
OUTCFG44
0x0 |
IRPTEN44
0x0 |
RDZERO44
0x0 |
INPEN44
0x0 |
FNCSEL44
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN44 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN44 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL44 | RW | Polarity select for NCE for GPIO 44 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC44 | RW | IOMSTR/MSPI N Chip Select 44, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG44 | RW | Pullup/Pulldown configuration for GPIO 44 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR44 | RW | Configure the slew rate |
| 11:10 | DS44 | RW | Drive strength selection for GPIO 44 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG44 | RW | Pin IO mode selection for GPIO pin 44 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN44 | RW | Interrupt enable for GPIO 44 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO44 | RW | Return 0 for read data on GPIO 44 |
| 4 | INPEN44 | RW | Input enable for GPIO 44 |
| 3:0 | FNCSEL44 | RW | Function select for GPIO pin 44 MSPI1_7 = 0x0 - MSPI Master 1 Interface Signal TRIG1 = 0x1 - ADC trigger input SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) DISP_D22 = 0x5 - Display Data 22 CT44 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE44 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS12 = 0x8 - Observation bus bit 12 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100B4 |
Controls the operation of GPIO pin 45.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN45
0x0 |
FIEN45
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL45
0x0 |
NCESRC45
0x0 |
PULLCFG45
0x0 |
SR45
0x0 |
DS45
0x0 |
OUTCFG45
0x0 |
IRPTEN45
0x0 |
RDZERO45
0x0 |
INPEN45
0x0 |
FNCSEL45
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN45 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN45 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL45 | RW | Polarity select for NCE for GPIO 45 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC45 | RW | IOMSTR/MSPI N Chip Select 45, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG45 | RW | Pullup/Pulldown configuration for GPIO 45 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR45 | RW | Configure the slew rate |
| 11:10 | DS45 | RW | Drive strength selection for GPIO 45 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG45 | RW | Pin IO mode selection for GPIO pin 45 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN45 | RW | Interrupt enable for GPIO 45 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO45 | RW | Return 0 for read data on GPIO 45 |
| 4 | INPEN45 | RW | Input enable for GPIO 45 |
| 3:0 | FNCSEL45 | RW | Function select for GPIO pin 45 MSPI1_8 = 0x0 - MSPI Master 1 Interface Signal TRIG2 = 0x1 - ADC trigger input 32KHzXT = 0x2 - 32kHZ from analog GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) DISP_D23 = 0x5 - Display Data 23 CT45 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE45 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS13 = 0x8 - Observation bus bit 13 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100B8 |
Controls the operation of GPIO pin 46.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN46
0x0 |
FIEN46
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL46
0x0 |
NCESRC46
0x0 |
PULLCFG46
0x0 |
SR46
0x0 |
DS46
0x0 |
OUTCFG46
0x0 |
IRPTEN46
0x0 |
RDZERO46
0x0 |
INPEN46
0x0 |
FNCSEL46
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN46 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN46 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL46 | RW | Polarity select for NCE for GPIO 46 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC46 | RW | IOMSTR/MSPI N Chip Select 46, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG46 | RW | Pullup/Pulldown configuration for GPIO 46 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR46 | RW | Configure the slew rate |
| 11:10 | DS46 | RW | Drive strength selection for GPIO 46 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG46 | RW | Pin IO mode selection for GPIO pin 46 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN46 | RW | Interrupt enable for GPIO 46 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO46 | RW | Return 0 for read data on GPIO 46 |
| 4 | INPEN46 | RW | Input enable for GPIO 46 |
| 3:0 | FNCSEL46 | RW | Function select for GPIO pin 46 MSPI1_9 = 0x0 - MSPI Master 1 Interface Signal TRIG3 = 0x1 - ADC trigger input CLKOUT_32M = 0x2 - 32MHz Oscillator output clock GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) UART3TX = 0x5 - UART transmit output (UART 3) CT46 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE46 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS14 = 0x8 - Observation bus bit 14 I2S1_SDIN = 0x9 - I2S Data input (I2S Master/Slave 2) I2S0_SDIN = 0xA - I2S Data input (I2S Master/Slave 2) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100BC |
Controls the operation of GPIO pin 47.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN47
0x0 |
FIEN47
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL47
0x0 |
NCESRC47
0x0 |
PULLCFG47
0x0 |
SR47
0x0 |
DS47
0x0 |
OUTCFG47
0x0 |
IRPTEN47
0x0 |
RDZERO47
0x0 |
INPEN47
0x0 |
FNCSEL47
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN47 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN47 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL47 | RW | Polarity select for NCE for GPIO 47 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC47 | RW | IOMSTR/MSPI N Chip Select 47, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG47 | RW | Pullup/Pulldown configuration for GPIO 47 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR47 | RW | Configure the slew rate |
| 11:10 | DS47 | RW | Drive strength selection for GPIO 47 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG47 | RW | Pin IO mode selection for GPIO pin 47 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN47 | RW | Interrupt enable for GPIO 47 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO47 | RW | Return 0 for read data on GPIO 47 |
| 4 | INPEN47 | RW | Input enable for GPIO 47 |
| 3:0 | FNCSEL47 | RW | Function select for GPIO pin 47 M5SCL = 0x0 - Serial I2C Master Clock output (IOM 5) M5SCK = 0x1 - Serial SPI Master Clock output (IOM 5) I2S1_CLK = 0x2 - Bidirectional I2S Bit clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) UART1RX = 0x5 - UART receive input (UART 1) CT47 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE47 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS15 = 0x8 - Observation bus bit 15 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. I2S0_CLK = 0xA - Bidirectional I2S Bit clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100C0 |
Controls the operation of GPIO pin 48.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN48
0x0 |
FIEN48
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL48
0x0 |
NCESRC48
0x0 |
PULLCFG48
0x0 |
SR48
0x0 |
DS48
0x0 |
OUTCFG48
0x0 |
IRPTEN48
0x0 |
RDZERO48
0x0 |
INPEN48
0x0 |
FNCSEL48
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN48 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN48 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL48 | RW | Polarity select for NCE for GPIO 48 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC48 | RW | IOMSTR/MSPI N Chip Select 48, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG48 | RW | Pullup/Pulldown configuration for GPIO 48 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR48 | RW | Configure the slew rate |
| 11:10 | DS48 | RW | Drive strength selection for GPIO 48 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG48 | RW | Pin IO mode selection for GPIO pin 48 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN48 | RW | Interrupt enable for GPIO 48 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO48 | RW | Return 0 for read data on GPIO 48 |
| 4 | INPEN48 | RW | Input enable for GPIO 48 |
| 3:0 | FNCSEL48 | RW | Function select for GPIO pin 48 M5SDAWIR3 = 0x0 - Serial I2C Master Data I/O (I2C Mode) Serial SPI Master Data I/O (SPI 3 wire mode) (IOM 5) M5MOSI = 0x1 - Serial SPI Master MOSI output (IOM 5) I2S1_DATA = 0x2 - Bidirectional I2S Data. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) UART3RX = 0x5 - UART receive input (UART 3) CT48 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE48 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS0 = 0x8 - Observation bus bit 0 I2S1_SDOUT = 0x9 - I2S Data output (I2S Master/Slave 2) I2S0_SDOUT = 0xA - I2S Data output (I2S Master/Slave 2) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100C4 |
Controls the operation of GPIO pin 49.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN49
0x0 |
FIEN49
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL49
0x0 |
NCESRC49
0x0 |
PULLCFG49
0x0 |
SR49
0x0 |
DS49
0x0 |
OUTCFG49
0x0 |
IRPTEN49
0x0 |
RDZERO49
0x0 |
INPEN49
0x0 |
FNCSEL49
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN49 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN49 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL49 | RW | Polarity select for NCE for GPIO 49 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC49 | RW | IOMSTR/MSPI N Chip Select 49, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG49 | RW | Pullup/Pulldown configuration for GPIO 49 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR49 | RW | Configure the slew rate |
| 11:10 | DS49 | RW | Drive strength selection for GPIO 49 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG49 | RW | Pin IO mode selection for GPIO pin 49 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN49 | RW | Interrupt enable for GPIO 49 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO49 | RW | Return 0 for read data on GPIO 49 |
| 4 | INPEN49 | RW | Input enable for GPIO 49 |
| 3:0 | FNCSEL49 | RW | Function select for GPIO pin 49 M5MISO = 0x0 - Serial SPI MASTER MISO input (IOM 5) TRIG0 = 0x1 - ADC trigger input I2S1_WS = 0x2 - Bidirectional I2S L/R clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART0RTS = 0x4 - UART Request to Send (RTS) (UART 0) UART1RTS = 0x5 - UART Request to Send (RTS) (UART 1) CT49 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE49 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS1 = 0x8 - Observation bus bit 1 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. I2S0_WS = 0xA - Bidirectional I2S L/R clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100C8 |
Controls the operation of GPIO pin 50.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN50
0x0 |
FIEN50
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL50
0x0 |
NCESRC50
0x0 |
PULLCFG50
0x0 |
SR50
0x0 |
DS50
0x0 |
OUTCFG50
0x0 |
IRPTEN50
0x0 |
RDZERO50
0x0 |
INPEN50
0x0 |
FNCSEL50
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN50 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN50 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL50 | RW | Polarity select for NCE for GPIO 50 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC50 | RW | IOMSTR/MSPI N Chip Select 50, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG50 | RW | Pullup/Pulldown configuration for GPIO 50 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR50 | RW | Configure the slew rate |
| 11:10 | DS50 | RW | Drive strength selection for GPIO 50 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG50 | RW | Pin IO mode selection for GPIO pin 50 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN50 | RW | Interrupt enable for GPIO 50 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO50 | RW | Return 0 for read data on GPIO 50 |
| 4 | INPEN50 | RW | Input enable for GPIO 50 |
| 3:0 | FNCSEL50 | RW | Function select for GPIO pin 50 PDM0_CLK = 0x0 - PDMx Clock output (I2C Master/Slave D) TRIG0 = 0x1 - ADC trigger input SWTRACECLK = 0x2 - Serial Wire Debug Trace Clock GPIO = 0x3 - General purpose I/O UART2RTS = 0x4 - UART Request to Send (RTS) (UART 2) UART3RTS = 0x5 - UART Request to Send (RTS) (UART 3) CT50 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE50 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS2 = 0x8 - Observation bus bit 2 DISP_TE = 0x9 - Display TE input RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100CC |
Controls the operation of GPIO pin 51.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN51
0x0 |
FIEN51
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL51
0x0 |
NCESRC51
0x0 |
PULLCFG51
0x0 |
SR51
0x0 |
DS51
0x0 |
OUTCFG51
0x0 |
IRPTEN51
0x0 |
RDZERO51
0x0 |
INPEN51
0x0 |
FNCSEL51
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN51 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN51 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL51 | RW | Polarity select for NCE for GPIO 51 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC51 | RW | IOMSTR/MSPI N Chip Select 51, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG51 | RW | Pullup/Pulldown configuration for GPIO 51 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR51 | RW | Configure the slew rate |
| 11:10 | DS51 | RW | Drive strength selection for GPIO 51 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG51 | RW | Pin IO mode selection for GPIO pin 51 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN51 | RW | Interrupt enable for GPIO 51 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO51 | RW | Return 0 for read data on GPIO 51 |
| 4 | INPEN51 | RW | Input enable for GPIO 51 |
| 3:0 | FNCSEL51 | RW | Function select for GPIO pin 51 PDM0_DATA = 0x0 - PDMx audio data input to chip (I2C Master/Slave D) TRIG1 = 0x1 - ADC trigger input SWTRACE0 = 0x2 - Serial Wire Debug Trace Output 0 GPIO = 0x3 - General purpose I/O UART0CTS = 0x4 - UART Clear to Send (CTS) (UART 0) UART1CTS = 0x5 - UART Clear to Send (CTS) (UART 1) CT51 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE51 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS3 = 0x8 - Observation bus bit 3 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100D0 |
Controls the operation of GPIO pin 52.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN52
0x0 |
FIEN52
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL52
0x0 |
NCESRC52
0x0 |
PULLCFG52
0x0 |
SR52
0x0 |
DS52
0x0 |
OUTCFG52
0x0 |
IRPTEN52
0x0 |
RDZERO52
0x0 |
INPEN52
0x0 |
FNCSEL52
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN52 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN52 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL52 | RW | Polarity select for NCE for GPIO 52 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC52 | RW | IOMSTR/MSPI N Chip Select 52, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG52 | RW | Pullup/Pulldown configuration for GPIO 52 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR52 | RW | Configure the slew rate |
| 11:10 | DS52 | RW | Drive strength selection for GPIO 52 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG52 | RW | Pin IO mode selection for GPIO pin 52 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN52 | RW | Interrupt enable for GPIO 52 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO52 | RW | Return 0 for read data on GPIO 52 |
| 4 | INPEN52 | RW | Input enable for GPIO 52 |
| 3:0 | FNCSEL52 | RW | Function select for GPIO pin 52 PDM1_CLK = 0x0 - PDMx Clock output (I2C Master/Slave D) TRIG2 = 0x1 - ADC trigger input SWTRACE1 = 0x2 - Serial Wire Debug Trace Output 1 GPIO = 0x3 - General purpose I/O UART2CTS = 0x4 - UART Clear to Send (CTS) (UART 2) UART3CTS = 0x5 - UART Clear to Send (CTS) (UART 3) CT52 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE52 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS4 = 0x8 - Observation bus bit 4 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100D4 |
Controls the operation of GPIO pin 53.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN53
0x0 |
FIEN53
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL53
0x0 |
NCESRC53
0x0 |
PULLCFG53
0x0 |
SR53
0x0 |
DS53
0x0 |
OUTCFG53
0x0 |
IRPTEN53
0x0 |
RDZERO53
0x0 |
INPEN53
0x0 |
FNCSEL53
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN53 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN53 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL53 | RW | Polarity select for NCE for GPIO 53 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC53 | RW | IOMSTR/MSPI N Chip Select 53, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG53 | RW | Pullup/Pulldown configuration for GPIO 53 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR53 | RW | Configure the slew rate |
| 11:10 | DS53 | RW | Drive strength selection for GPIO 53 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG53 | RW | Pin IO mode selection for GPIO pin 53 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN53 | RW | Interrupt enable for GPIO 53 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO53 | RW | Return 0 for read data on GPIO 53 |
| 4 | INPEN53 | RW | Input enable for GPIO 53 |
| 3:0 | FNCSEL53 | RW | Function select for GPIO pin 53 PDM1_DATA = 0x0 - PDMx audio data input to chip (I2C Master/Slave D) TRIG3 = 0x1 - ADC trigger input SWTRACE2 = 0x2 - Serial Wire Debug Trace Output 2 GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) UART1TX = 0x5 - UART transmit output (UART 1) CT53 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE53 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS5 = 0x8 - Observation bus bit 5 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100D8 |
Controls the operation of GPIO pin 54.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN54
0x0 |
FIEN54
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL54
0x0 |
NCESRC54
0x0 |
PULLCFG54
0x0 |
SR54
0x0 |
DS54
0x0 |
OUTCFG54
0x0 |
IRPTEN54
0x0 |
RDZERO54
0x0 |
INPEN54
0x0 |
FNCSEL54
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN54 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN54 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL54 | RW | Polarity select for NCE for GPIO 54 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC54 | RW | IOMSTR/MSPI N Chip Select 54, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG54 | RW | Pullup/Pulldown configuration for GPIO 54 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR54 | RW | Configure the slew rate |
| 11:10 | DS54 | RW | Drive strength selection for GPIO 54 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG54 | RW | Pin IO mode selection for GPIO pin 54 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN54 | RW | Interrupt enable for GPIO 54 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO54 | RW | Return 0 for read data on GPIO 54 |
| 4 | INPEN54 | RW | Input enable for GPIO 54 |
| 3:0 | FNCSEL54 | RW | Function select for GPIO pin 54 PDM2_CLK = 0x0 - PDMx Clock output (I2C Master/Slave D) TRIG0 = 0x1 - ADC trigger input SWTRACE3 = 0x2 - Serial Wire Debug Trace Output 3 GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) UART3TX = 0x5 - UART transmit output (UART 3) CT54 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE54 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS6 = 0x8 - Observation bus bit 6 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100DC |
Controls the operation of GPIO pin 55.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN55
0x0 |
FIEN55
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL55
0x0 |
NCESRC55
0x0 |
PULLCFG55
0x0 |
SR55
0x0 |
DS55
0x0 |
OUTCFG55
0x0 |
IRPTEN55
0x0 |
RDZERO55
0x0 |
INPEN55
0x0 |
FNCSEL55
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN55 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN55 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL55 | RW | Polarity select for NCE for GPIO 55 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC55 | RW | IOMSTR/MSPI N Chip Select 55, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG55 | RW | Pullup/Pulldown configuration for GPIO 55 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR55 | RW | Configure the slew rate |
| 11:10 | DS55 | RW | Drive strength selection for GPIO 55 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG55 | RW | Pin IO mode selection for GPIO pin 55 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN55 | RW | Interrupt enable for GPIO 55 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO55 | RW | Return 0 for read data on GPIO 55 |
| 4 | INPEN55 | RW | Input enable for GPIO 55 |
| 3:0 | FNCSEL55 | RW | Function select for GPIO pin 55 PDM2_DATA = 0x0 - PDMx audio data input to chip (I2C Master/Slave D) TRIG1 = 0x1 - ADC trigger input SWTRACECTL = 0x2 - Serial Wire Debug Trace Control GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) UART1RX = 0x5 - UART receive input (UART 1) CT55 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE55 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS7 = 0x8 - Observation bus bit 7 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100E0 |
Controls the operation of GPIO pin 56.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN56
0x0 |
FIEN56
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL56
0x0 |
NCESRC56
0x0 |
PULLCFG56
0x0 |
SR56
0x0 |
DS56
0x0 |
OUTCFG56
0x0 |
IRPTEN56
0x0 |
RDZERO56
0x0 |
INPEN56
0x0 |
FNCSEL56
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN56 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN56 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL56 | RW | Polarity select for NCE for GPIO 56 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC56 | RW | IOMSTR/MSPI N Chip Select 56, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG56 | RW | Pullup/Pulldown configuration for GPIO 56 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR56 | RW | Configure the slew rate |
| 11:10 | DS56 | RW | Drive strength selection for GPIO 56 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG56 | RW | Pin IO mode selection for GPIO pin 56 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN56 | RW | Interrupt enable for GPIO 56 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO56 | RW | Return 0 for read data on GPIO 56 |
| 4 | INPEN56 | RW | Input enable for GPIO 56 |
| 3:0 | FNCSEL56 | RW | Function select for GPIO pin 56 PDM3_CLK = 0x0 - PDMx Clock output (I2C Master/Slave D) TRIG2 = 0x1 - ADC trigger input SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) UART3RX = 0x5 - UART receive input (UART 3) CT56 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE56 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS8 = 0x8 - Observation bus bit 8 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100E4 |
Controls the operation of GPIO pin 57.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN57
0x0 |
FIEN57
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL57
0x0 |
NCESRC57
0x0 |
PULLCFG57
0x0 |
SR57
0x0 |
DS57
0x0 |
OUTCFG57
0x0 |
IRPTEN57
0x0 |
RDZERO57
0x0 |
INPEN57
0x0 |
FNCSEL57
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN57 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN57 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL57 | RW | Polarity select for NCE for GPIO 57 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC57 | RW | IOMSTR/MSPI N Chip Select 57, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG57 | RW | Pullup/Pulldown configuration for GPIO 57 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR57 | RW | Configure the slew rate |
| 11:10 | DS57 | RW | Drive strength selection for GPIO 57 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG57 | RW | Pin IO mode selection for GPIO pin 57 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN57 | RW | Interrupt enable for GPIO 57 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO57 | RW | Return 0 for read data on GPIO 57 |
| 4 | INPEN57 | RW | Input enable for GPIO 57 |
| 3:0 | FNCSEL57 | RW | Function select for GPIO pin 57 PDM3_DATA = 0x0 - PDMx audio data input to chip (I2C Master/Slave D) TRIG3 = 0x1 - ADC trigger input SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART0RTS = 0x4 - UART Request to Send (RTS) (UART 0) UART1RTS = 0x5 - UART Request to Send (RTS) (UART 1) CT57 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE57 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS9 = 0x8 - Observation bus bit 9 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100E8 |
Controls the operation of GPIO pin 58.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN58
0x0 |
FIEN58
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL58
0x0 |
NCESRC58
0x0 |
PULLCFG58
0x0 |
SR58
0x0 |
DS58
0x0 |
OUTCFG58
0x0 |
IRPTEN58
0x0 |
RDZERO58
0x0 |
INPEN58
0x0 |
FNCSEL58
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN58 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN58 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL58 | RW | Polarity select for NCE for GPIO 58 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC58 | RW | IOMSTR/MSPI N Chip Select 58, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG58 | RW | Pullup/Pulldown configuration for GPIO 58 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR58 | RW | Configure the slew rate |
| 11:10 | DS58 | RW | Drive strength selection for GPIO 58 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG58 | RW | Pin IO mode selection for GPIO pin 58 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN58 | RW | Interrupt enable for GPIO 58 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO58 | RW | Return 0 for read data on GPIO 58 |
| 4 | INPEN58 | RW | Input enable for GPIO 58 |
| 3:0 | FNCSEL58 | RW | Function select for GPIO pin 58 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART0RTS = 0x4 - UART Request to Send (RTS) (UART 0) UART3RTS = 0x5 - UART Request to Send (RTS) (UART 3) CT58 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE58 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS10 = 0x8 - Observation bus bit 10 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100EC |
Controls the operation of GPIO pin 59.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN59
0x0 |
FIEN59
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL59
0x0 |
NCESRC59
0x0 |
PULLCFG59
0x0 |
SR59
0x0 |
DS59
0x0 |
OUTCFG59
0x0 |
IRPTEN59
0x0 |
RDZERO59
0x0 |
INPEN59
0x0 |
FNCSEL59
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN59 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN59 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL59 | RW | Polarity select for NCE for GPIO 59 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC59 | RW | IOMSTR/MSPI N Chip Select 59, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG59 | RW | Pullup/Pulldown configuration for GPIO 59 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR59 | RW | Configure the slew rate |
| 11:10 | DS59 | RW | Drive strength selection for GPIO 59 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG59 | RW | Pin IO mode selection for GPIO pin 59 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN59 | RW | Interrupt enable for GPIO 59 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO59 | RW | Return 0 for read data on GPIO 59 |
| 4 | INPEN59 | RW | Input enable for GPIO 59 |
| 3:0 | FNCSEL59 | RW | Function select for GPIO pin 59 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. TRIG0 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART0CTS = 0x4 - UART Clear to Send (CTS) (UART 0) UART1CTS = 0x5 - UART Clear to Send (CTS) (UART 1) CT59 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE59 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS11 = 0x8 - Observation bus bit 11 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100F0 |
Controls the operation of GPIO pin 60.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN60
0x0 |
FIEN60
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL60
0x0 |
NCESRC60
0x0 |
PULLCFG60
0x0 |
SR60
0x0 |
DS60
0x0 |
OUTCFG60
0x0 |
IRPTEN60
0x0 |
RDZERO60
0x0 |
INPEN60
0x0 |
FNCSEL60
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN60 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN60 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL60 | RW | Polarity select for NCE for GPIO 60 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC60 | RW | IOMSTR/MSPI N Chip Select 60, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG60 | RW | Pullup/Pulldown configuration for GPIO 60 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR60 | RW | Configure the slew rate |
| 11:10 | DS60 | RW | Drive strength selection for GPIO 60 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG60 | RW | Pin IO mode selection for GPIO pin 60 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN60 | RW | Interrupt enable for GPIO 60 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO60 | RW | Return 0 for read data on GPIO 60 |
| 4 | INPEN60 | RW | Input enable for GPIO 60 |
| 3:0 | FNCSEL60 | RW | Function select for GPIO pin 60 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. TRIG1 = 0x1 - ADC trigger input RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) UART3CTS = 0x5 - UART Clear to Send (CTS) (UART 3) CT60 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE60 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS12 = 0x8 - Observation bus bit 12 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100F4 |
Controls the operation of GPIO pin 61.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN61
0x0 |
FIEN61
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL61
0x0 |
NCESRC61
0x0 |
PULLCFG61
0x0 |
SR61
0x0 |
DS61
0x0 |
OUTCFG61
0x0 |
IRPTEN61
0x0 |
RDZERO61
0x0 |
INPEN61
0x0 |
FNCSEL61
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN61 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN61 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL61 | RW | Polarity select for NCE for GPIO 61 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC61 | RW | IOMSTR/MSPI N Chip Select 61, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG61 | RW | Pullup/Pulldown configuration for GPIO 61 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR61 | RW | Configure the slew rate |
| 11:10 | DS61 | RW | Drive strength selection for GPIO 61 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG61 | RW | Pin IO mode selection for GPIO pin 61 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN61 | RW | Interrupt enable for GPIO 61 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO61 | RW | Return 0 for read data on GPIO 61 |
| 4 | INPEN61 | RW | Input enable for GPIO 61 |
| 3:0 | FNCSEL61 | RW | Function select for GPIO pin 61 M6SCL = 0x0 - Serial I2C Master Clock output (IOM 6) M6SCK = 0x1 - Serial SPI Master Clock output (IOM 6) I2S1_CLK = 0x2 - Bidirectional I2S Bit clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) UART3TX = 0x5 - UART transmit output (UART 3) CT61 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE61 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS13 = 0x8 - Observation bus bit 13 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. I3CM0_SCL = 0xA - Serial I3C Master Clock output (IOM 0) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100F8 |
Controls the operation of GPIO pin 62.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN62
0x0 |
FIEN62
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL62
0x0 |
NCESRC62
0x0 |
PULLCFG62
0x0 |
SR62
0x0 |
DS62
0x0 |
OUTCFG62
0x0 |
IRPTEN62
0x0 |
RDZERO62
0x0 |
INPEN62
0x0 |
FNCSEL62
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN62 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN62 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL62 | RW | Polarity select for NCE for GPIO 62 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC62 | RW | IOMSTR/MSPI N Chip Select 62, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG62 | RW | Pullup/Pulldown configuration for GPIO 62 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR62 | RW | Configure the slew rate |
| 11:10 | DS62 | RW | Drive strength selection for GPIO 62 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG62 | RW | Pin IO mode selection for GPIO pin 62 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN62 | RW | Interrupt enable for GPIO 62 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO62 | RW | Return 0 for read data on GPIO 62 |
| 4 | INPEN62 | RW | Input enable for GPIO 62 |
| 3:0 | FNCSEL62 | RW | Function select for GPIO pin 62 M6SDAWIR3 = 0x0 - Serial I2C Master Data I/O (I2C Mode) Serial SPI Master Data I/O (SPI 3 wire mode) (IOM 6) M6MOSI = 0x1 - Serial SPI Master MOSI output (IOM 6) I2S1_DATA = 0x2 - Bidirectional I2S Data. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) UART1RX = 0x5 - UART receive input (UART 1) CT62 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE62 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS14 = 0x8 - Observation bus bit 14 I2S1_SDOUT = 0x9 - I2S Data output (I2S Master/Slave 2) I3CM0_SDA = 0xA - Serial I3C Master Data I/O (IOM 0) FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400100FC |
Controls the operation of GPIO pin 63.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN63
0x0 |
FIEN63
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL63
0x0 |
NCESRC63
0x0 |
PULLCFG63
0x0 |
SR63
0x0 |
DS63
0x0 |
OUTCFG63
0x0 |
IRPTEN63
0x0 |
RDZERO63
0x0 |
INPEN63
0x0 |
FNCSEL63
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN63 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN63 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL63 | RW | Polarity select for NCE for GPIO 63 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC63 | RW | IOMSTR/MSPI N Chip Select 63, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG63 | RW | Pullup/Pulldown configuration for GPIO 63 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR63 | RW | Configure the slew rate |
| 11:10 | DS63 | RW | Drive strength selection for GPIO 63 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG63 | RW | Pin IO mode selection for GPIO pin 63 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN63 | RW | Interrupt enable for GPIO 63 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO63 | RW | Return 0 for read data on GPIO 63 |
| 4 | INPEN63 | RW | Input enable for GPIO 63 |
| 3:0 | FNCSEL63 | RW | Function select for GPIO pin 63 M6MISO = 0x0 - Serial SPI MASTER MISO input (IOM 6) CLKOUT = 0x1 - Oscillator output clock I2S1_WS = 0x2 - Bidirectional I2S L/R clock. Operates in output mode in master mode and input mode for slave mode. (I2S Master/Slave 2) GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) UART3RX = 0x5 - UART receive input (UART 3) CT63 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE63 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS15 = 0x8 - Observation bus bit 15 DISP_TE = 0x9 - Display TE input RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010100 |
Controls the operation of GPIO pin 64.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN64
0x0 |
FIEN64
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL64
0x0 |
NCESRC64
0x0 |
PULLCFG64
0x0 |
SR64
0x0 |
DS64
0x0 |
OUTCFG64
0x0 |
IRPTEN64
0x0 |
RDZERO64
0x0 |
INPEN64
0x0 |
FNCSEL64
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN64 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN64 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL64 | RW | Polarity select for NCE for GPIO 64 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC64 | RW | IOMSTR/MSPI N Chip Select 64, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG64 | RW | Pullup/Pulldown configuration for GPIO 64 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR64 | RW | Configure the slew rate |
| 11:10 | DS64 | RW | Drive strength selection for GPIO 64 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG64 | RW | Pin IO mode selection for GPIO pin 64 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN64 | RW | Interrupt enable for GPIO 64 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO64 | RW | Return 0 for read data on GPIO 64 |
| 4 | INPEN64 | RW | Input enable for GPIO 64 |
| 3:0 | FNCSEL64 | RW | Function select for GPIO pin 64 MSPI0_0 = 0x0 - MSPI Master 0 Interface Signal 32KHzXT = 0x1 - 32kHZ from analog SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART0RTS = 0x4 - UART Request to Send (RTS) (UART 0) DISP_D0 = 0x5 - Display Data 0 CT64 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE64 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS0 = 0x8 - Observation bus bit 0 I2S1_SDIN = 0x9 - I2S Data input (I2S Master/Slave 2) RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010104 |
Controls the operation of GPIO pin 65.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN65
0x0 |
FIEN65
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL65
0x0 |
NCESRC65
0x0 |
PULLCFG65
0x0 |
SR65
0x0 |
DS65
0x0 |
OUTCFG65
0x0 |
IRPTEN65
0x0 |
RDZERO65
0x0 |
INPEN65
0x0 |
FNCSEL65
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN65 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN65 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL65 | RW | Polarity select for NCE for GPIO 65 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC65 | RW | IOMSTR/MSPI N Chip Select 65, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG65 | RW | Pullup/Pulldown configuration for GPIO 65 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR65 | RW | Configure the slew rate |
| 11:10 | DS65 | RW | Drive strength selection for GPIO 65 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG65 | RW | Pin IO mode selection for GPIO pin 65 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN65 | RW | Interrupt enable for GPIO 65 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO65 | RW | Return 0 for read data on GPIO 65 |
| 4 | INPEN65 | RW | Input enable for GPIO 65 |
| 3:0 | FNCSEL65 | RW | Function select for GPIO pin 65 MSPI0_1 = 0x0 - MSPI Master 0 Interface Signal 32KHzXT = 0x1 - 32kHZ from analog SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART0CTS = 0x4 - UART Clear to Send (CTS) (UART 0) DISP_D1 = 0x5 - Display Data 1 CT65 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE65 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS1 = 0x8 - Observation bus bit 1 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010108 |
Controls the operation of GPIO pin 66.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN66
0x0 |
FIEN66
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL66
0x0 |
NCESRC66
0x0 |
PULLCFG66
0x0 |
SR66
0x0 |
DS66
0x0 |
OUTCFG66
0x0 |
IRPTEN66
0x0 |
RDZERO66
0x0 |
INPEN66
0x0 |
FNCSEL66
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN66 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN66 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL66 | RW | Polarity select for NCE for GPIO 66 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC66 | RW | IOMSTR/MSPI N Chip Select 66, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG66 | RW | Pullup/Pulldown configuration for GPIO 66 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR66 | RW | Configure the slew rate |
| 11:10 | DS66 | RW | Drive strength selection for GPIO 66 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG66 | RW | Pin IO mode selection for GPIO pin 66 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN66 | RW | Interrupt enable for GPIO 66 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO66 | RW | Return 0 for read data on GPIO 66 |
| 4 | INPEN66 | RW | Input enable for GPIO 66 |
| 3:0 | FNCSEL66 | RW | Function select for GPIO pin 66 MSPI0_2 = 0x0 - MSPI Master 0 Interface Signal CLKOUT = 0x1 - Oscillator output clock SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) DISP_D2 = 0x5 - Display Data 2 CT66 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE66 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS2 = 0x8 - Observation bus bit 2 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001010C |
Controls the operation of GPIO pin 67.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN67
0x0 |
FIEN67
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL67
0x0 |
NCESRC67
0x0 |
PULLCFG67
0x0 |
SR67
0x0 |
DS67
0x0 |
OUTCFG67
0x0 |
IRPTEN67
0x0 |
RDZERO67
0x0 |
INPEN67
0x0 |
FNCSEL67
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN67 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN67 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL67 | RW | Polarity select for NCE for GPIO 67 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC67 | RW | IOMSTR/MSPI N Chip Select 67, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG67 | RW | Pullup/Pulldown configuration for GPIO 67 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR67 | RW | Configure the slew rate |
| 11:10 | DS67 | RW | Drive strength selection for GPIO 67 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG67 | RW | Pin IO mode selection for GPIO pin 67 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN67 | RW | Interrupt enable for GPIO 67 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO67 | RW | Return 0 for read data on GPIO 67 |
| 4 | INPEN67 | RW | Input enable for GPIO 67 |
| 3:0 | FNCSEL67 | RW | Function select for GPIO pin 67 MSPI0_3 = 0x0 - MSPI Master 0 Interface Signal CLKOUT = 0x1 - Oscillator output clock SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) DISP_D3 = 0x5 - Display Data 3 CT67 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE67 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS3 = 0x8 - Observation bus bit 3 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010110 |
Controls the operation of GPIO pin 68.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN68
0x0 |
FIEN68
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL68
0x0 |
NCESRC68
0x0 |
PULLCFG68
0x0 |
SR68
0x0 |
DS68
0x0 |
OUTCFG68
0x0 |
IRPTEN68
0x0 |
RDZERO68
0x0 |
INPEN68
0x0 |
FNCSEL68
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN68 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN68 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL68 | RW | Polarity select for NCE for GPIO 68 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC68 | RW | IOMSTR/MSPI N Chip Select 68, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG68 | RW | Pullup/Pulldown configuration for GPIO 68 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR68 | RW | Configure the slew rate |
| 11:10 | DS68 | RW | Drive strength selection for GPIO 68 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG68 | RW | Pin IO mode selection for GPIO pin 68 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN68 | RW | Interrupt enable for GPIO 68 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO68 | RW | Return 0 for read data on GPIO 68 |
| 4 | INPEN68 | RW | Input enable for GPIO 68 |
| 3:0 | FNCSEL68 | RW | Function select for GPIO pin 68 MSPI0_4 = 0x0 - MSPI Master 0 Interface Signal SWO = 0x1 - Serial Wire Output RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) DISP_D4 = 0x5 - Display Data 4 CT68 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE68 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS4 = 0x8 - Observation bus bit 4 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010114 |
Controls the operation of GPIO pin 69.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN69
0x0 |
FIEN69
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL69
0x0 |
NCESRC69
0x0 |
PULLCFG69
0x0 |
SR69
0x0 |
DS69
0x0 |
OUTCFG69
0x0 |
IRPTEN69
0x0 |
RDZERO69
0x0 |
INPEN69
0x0 |
FNCSEL69
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN69 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN69 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL69 | RW | Polarity select for NCE for GPIO 69 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC69 | RW | IOMSTR/MSPI N Chip Select 69, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG69 | RW | Pullup/Pulldown configuration for GPIO 69 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR69 | RW | Configure the slew rate |
| 11:10 | DS69 | RW | Drive strength selection for GPIO 69 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG69 | RW | Pin IO mode selection for GPIO pin 69 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN69 | RW | Interrupt enable for GPIO 69 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO69 | RW | Return 0 for read data on GPIO 69 |
| 4 | INPEN69 | RW | Input enable for GPIO 69 |
| 3:0 | FNCSEL69 | RW | Function select for GPIO pin 69 MSPI0_5 = 0x0 - MSPI Master 0 Interface Signal 32KHzXT = 0x1 - 32kHZ from analog SWO = 0x2 - Serial Wire Output GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) DISP_D5 = 0x5 - Display Data 5 CT69 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE69 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS5 = 0x8 - Observation bus bit 5 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010118 |
Controls the operation of GPIO pin 70.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN70
0x0 |
FIEN70
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL70
0x0 |
NCESRC70
0x0 |
PULLCFG70
0x0 |
SR70
0x0 |
DS70
0x0 |
OUTCFG70
0x0 |
IRPTEN70
0x0 |
RDZERO70
0x0 |
INPEN70
0x0 |
FNCSEL70
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN70 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN70 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL70 | RW | Polarity select for NCE for GPIO 70 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC70 | RW | IOMSTR/MSPI N Chip Select 70, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG70 | RW | Pullup/Pulldown configuration for GPIO 70 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR70 | RW | Configure the slew rate |
| 11:10 | DS70 | RW | Drive strength selection for GPIO 70 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG70 | RW | Pin IO mode selection for GPIO pin 70 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN70 | RW | Interrupt enable for GPIO 70 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO70 | RW | Return 0 for read data on GPIO 70 |
| 4 | INPEN70 | RW | Input enable for GPIO 70 |
| 3:0 | FNCSEL70 | RW | Function select for GPIO pin 70 MSPI0_6 = 0x0 - MSPI Master 0 Interface Signal 32KHzXT = 0x1 - 32kHZ from analog SWTRACE0 = 0x2 - Serial Wire Debug Trace Output 0 GPIO = 0x3 - General purpose I/O UART0RTS = 0x4 - UART Request to Send (RTS) (UART 0) DISP_D6 = 0x5 - Display Data 6 CT70 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE70 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS6 = 0x8 - Observation bus bit 6 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001011C |
Controls the operation of GPIO pin 71.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN71
0x0 |
FIEN71
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL71
0x0 |
NCESRC71
0x0 |
PULLCFG71
0x0 |
SR71
0x0 |
DS71
0x0 |
OUTCFG71
0x0 |
IRPTEN71
0x0 |
RDZERO71
0x0 |
INPEN71
0x0 |
FNCSEL71
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN71 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN71 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL71 | RW | Polarity select for NCE for GPIO 71 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC71 | RW | IOMSTR/MSPI N Chip Select 71, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG71 | RW | Pullup/Pulldown configuration for GPIO 71 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR71 | RW | Configure the slew rate |
| 11:10 | DS71 | RW | Drive strength selection for GPIO 71 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG71 | RW | Pin IO mode selection for GPIO pin 71 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN71 | RW | Interrupt enable for GPIO 71 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO71 | RW | Return 0 for read data on GPIO 71 |
| 4 | INPEN71 | RW | Input enable for GPIO 71 |
| 3:0 | FNCSEL71 | RW | Function select for GPIO pin 71 MSPI0_7 = 0x0 - MSPI Master 0 Interface Signal CLKOUT = 0x1 - Oscillator output clock SWTRACE1 = 0x2 - Serial Wire Debug Trace Output 1 GPIO = 0x3 - General purpose I/O UART0CTS = 0x4 - UART Clear to Send (CTS) (UART 0) DISP_D7 = 0x5 - Display Data 7 CT71 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE71 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS7 = 0x8 - Observation bus bit 7 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010120 |
Controls the operation of GPIO pin 72.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN72
0x0 |
FIEN72
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL72
0x0 |
NCESRC72
0x0 |
PULLCFG72
0x0 |
SR72
0x0 |
DS72
0x0 |
OUTCFG72
0x0 |
IRPTEN72
0x0 |
RDZERO72
0x0 |
INPEN72
0x0 |
FNCSEL72
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN72 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN72 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL72 | RW | Polarity select for NCE for GPIO 72 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC72 | RW | IOMSTR/MSPI N Chip Select 72, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG72 | RW | Pullup/Pulldown configuration for GPIO 72 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR72 | RW | Configure the slew rate |
| 11:10 | DS72 | RW | Drive strength selection for GPIO 72 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG72 | RW | Pin IO mode selection for GPIO pin 72 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN72 | RW | Interrupt enable for GPIO 72 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO72 | RW | Return 0 for read data on GPIO 72 |
| 4 | INPEN72 | RW | Input enable for GPIO 72 |
| 3:0 | FNCSEL72 | RW | Function select for GPIO pin 72 MSPI0_8 = 0x0 - MSPI Master 0 Interface Signal CLKOUT = 0x1 - Oscillator output clock SWTRACE2 = 0x2 - Serial Wire Debug Trace Output 2 GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) DISP_D8 = 0x5 - Display Data 8 CT72 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE72 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS8 = 0x8 - Observation bus bit 8 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010124 |
Controls the operation of GPIO pin 73.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN73
0x0 |
FIEN73
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL73
0x0 |
NCESRC73
0x0 |
PULLCFG73
0x0 |
SR73
0x0 |
DS73
0x0 |
OUTCFG73
0x0 |
IRPTEN73
0x0 |
RDZERO73
0x0 |
INPEN73
0x0 |
FNCSEL73
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN73 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN73 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL73 | RW | Polarity select for NCE for GPIO 73 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC73 | RW | IOMSTR/MSPI N Chip Select 73, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG73 | RW | Pullup/Pulldown configuration for GPIO 73 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR73 | RW | Configure the slew rate |
| 11:10 | DS73 | RW | Drive strength selection for GPIO 73 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG73 | RW | Pin IO mode selection for GPIO pin 73 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN73 | RW | Interrupt enable for GPIO 73 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO73 | RW | Return 0 for read data on GPIO 73 |
| 4 | INPEN73 | RW | Input enable for GPIO 73 |
| 3:0 | FNCSEL73 | RW | Function select for GPIO pin 73 MSPI0_9 = 0x0 - MSPI Master 0 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. SWTRACE3 = 0x2 - Serial Wire Debug Trace Output 3 GPIO = 0x3 - General purpose I/O UART2TX = 0x4 - UART transmit output (UART 2) DISP_D9 = 0x5 - Display Data 9 CT73 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE73 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS9 = 0x8 - Observation bus bit 9 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010128 |
Controls the operation of GPIO pin 74.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN74
0x0 |
FIEN74
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL74
0x0 |
NCESRC74
0x0 |
PULLCFG74
0x0 |
SR74
0x0 |
DS74
0x0 |
OUTCFG74
0x0 |
IRPTEN74
0x0 |
RDZERO74
0x0 |
INPEN74
0x0 |
FNCSEL74
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN74 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN74 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL74 | RW | Polarity select for NCE for GPIO 74 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC74 | RW | IOMSTR/MSPI N Chip Select 74, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG74 | RW | Pullup/Pulldown configuration for GPIO 74 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR74 | RW | Configure the slew rate |
| 11:10 | DS74 | RW | Drive strength selection for GPIO 74 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG74 | RW | Pin IO mode selection for GPIO pin 74 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN74 | RW | Interrupt enable for GPIO 74 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO74 | RW | Return 0 for read data on GPIO 74 |
| 4 | INPEN74 | RW | Input enable for GPIO 74 |
| 3:0 | FNCSEL74 | RW | Function select for GPIO pin 74 MSPI2_0 = 0x0 - MSPI Master 2 Interface Signal DISP_QSPI_D0_OUT = 0x1 - Display SPI Data0 DISP_QSPI_D0 = 0x2 - Display SPI Data0 GPIO = 0x3 - General purpose I/O UART0RX = 0x4 - UART receive input (UART 0) DISP_D10 = 0x5 - Display Data 10 CT74 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE74 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS10 = 0x8 - Observation bus bit 10 DISP_SPI_SD = 0x9 - Display SPI Data Out DISP_SPI_SDO = 0xA - Display SPI Data Out FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001012C |
Controls the operation of GPIO pin 75.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN75
0x0 |
FIEN75
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL75
0x0 |
NCESRC75
0x0 |
PULLCFG75
0x0 |
SR75
0x0 |
DS75
0x0 |
OUTCFG75
0x0 |
IRPTEN75
0x0 |
RDZERO75
0x0 |
INPEN75
0x0 |
FNCSEL75
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN75 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN75 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL75 | RW | Polarity select for NCE for GPIO 75 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC75 | RW | IOMSTR/MSPI N Chip Select 75, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG75 | RW | Pullup/Pulldown configuration for GPIO 75 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR75 | RW | Configure the slew rate |
| 11:10 | DS75 | RW | Drive strength selection for GPIO 75 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG75 | RW | Pin IO mode selection for GPIO pin 75 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN75 | RW | Interrupt enable for GPIO 75 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO75 | RW | Return 0 for read data on GPIO 75 |
| 4 | INPEN75 | RW | Input enable for GPIO 75 |
| 3:0 | FNCSEL75 | RW | Function select for GPIO pin 75 MSPI2_1 = 0x0 - MSPI Master 2 Interface Signal 32KHzXT = 0x1 - 32kHZ from analog DISP_QSPI_D1 = 0x2 - Display SPI Data1 GPIO = 0x3 - General purpose I/O UART2RX = 0x4 - UART receive input (UART 2) DISP_D11 = 0x5 - Display Data 11 CT75 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE75 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS11 = 0x8 - Observation bus bit 11 DISP_SPI_DCX = 0x9 - Display SPI DCx RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010130 |
Controls the operation of GPIO pin 76.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN76
0x0 |
FIEN76
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL76
0x0 |
NCESRC76
0x0 |
PULLCFG76
0x0 |
SR76
0x0 |
DS76
0x0 |
OUTCFG76
0x0 |
IRPTEN76
0x0 |
RDZERO76
0x0 |
INPEN76
0x0 |
FNCSEL76
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN76 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN76 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL76 | RW | Polarity select for NCE for GPIO 76 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC76 | RW | IOMSTR/MSPI N Chip Select 76, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG76 | RW | Pullup/Pulldown configuration for GPIO 76 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR76 | RW | Configure the slew rate |
| 11:10 | DS76 | RW | Drive strength selection for GPIO 76 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG76 | RW | Pin IO mode selection for GPIO pin 76 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN76 | RW | Interrupt enable for GPIO 76 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO76 | RW | Return 0 for read data on GPIO 76 |
| 4 | INPEN76 | RW | Input enable for GPIO 76 |
| 3:0 | FNCSEL76 | RW | Function select for GPIO pin 76 MSPI2_2 = 0x0 - MSPI Master 2 Interface Signal 32KHzXT = 0x1 - 32kHZ from analog DISP_QSPI_D2 = 0x2 - Display SPI Data2 GPIO = 0x3 - General purpose I/O UART0RTS = 0x4 - UART Request to Send (RTS) (UART 0) DISP_D12 = 0x5 - Display Data 12 CT76 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE76 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS12 = 0x8 - Observation bus bit 12 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010134 |
Controls the operation of GPIO pin 77.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN77
0x0 |
FIEN77
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL77
0x0 |
NCESRC77
0x0 |
PULLCFG77
0x0 |
SR77
0x0 |
DS77
0x0 |
OUTCFG77
0x0 |
IRPTEN77
0x0 |
RDZERO77
0x0 |
INPEN77
0x0 |
FNCSEL77
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN77 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN77 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL77 | RW | Polarity select for NCE for GPIO 77 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC77 | RW | IOMSTR/MSPI N Chip Select 77, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG77 | RW | Pullup/Pulldown configuration for GPIO 77 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR77 | RW | Configure the slew rate |
| 11:10 | DS77 | RW | Drive strength selection for GPIO 77 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG77 | RW | Pin IO mode selection for GPIO pin 77 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN77 | RW | Interrupt enable for GPIO 77 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO77 | RW | Return 0 for read data on GPIO 77 |
| 4 | INPEN77 | RW | Input enable for GPIO 77 |
| 3:0 | FNCSEL77 | RW | Function select for GPIO pin 77 MSPI2_3 = 0x0 - MSPI Master 2 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. DISP_QSPI_D3 = 0x2 - Display SPI Data3 GPIO = 0x3 - General purpose I/O UART0CTS = 0x4 - UART Clear to Send (CTS) (UART 0) DISP_D13 = 0x5 - Display Data 13 CT77 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE77 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS13 = 0x8 - Observation bus bit 13 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010138 |
Controls the operation of GPIO pin 78.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN78
0x0 |
FIEN78
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL78
0x0 |
NCESRC78
0x0 |
PULLCFG78
0x0 |
SR78
0x0 |
DS78
0x0 |
OUTCFG78
0x0 |
IRPTEN78
0x0 |
RDZERO78
0x0 |
INPEN78
0x0 |
FNCSEL78
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN78 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN78 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL78 | RW | Polarity select for NCE for GPIO 78 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC78 | RW | IOMSTR/MSPI N Chip Select 78, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG78 | RW | Pullup/Pulldown configuration for GPIO 78 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR78 | RW | Configure the slew rate |
| 11:10 | DS78 | RW | Drive strength selection for GPIO 78 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG78 | RW | Pin IO mode selection for GPIO pin 78 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN78 | RW | Interrupt enable for GPIO 78 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO78 | RW | Return 0 for read data on GPIO 78 |
| 4 | INPEN78 | RW | Input enable for GPIO 78 |
| 3:0 | FNCSEL78 | RW | Function select for GPIO pin 78 MSPI2_4 = 0x0 - MSPI Master 2 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. DISP_QSPI_SCK = 0x2 - Display SPI CLK GPIO = 0x3 - General purpose I/O UART0TX = 0x4 - UART transmit output (UART 0) DISP_D14 = 0x5 - Display Data 14 CT78 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE78 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS14 = 0x8 - Observation bus bit 14 DISP_SPI_SCK = 0x9 - Display SPI Clock RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001013C |
Controls the operation of GPIO pin 79.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN79
0x0 |
FIEN79
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL79
0x0 |
NCESRC79
0x0 |
PULLCFG79
0x0 |
SR79
0x0 |
DS79
0x0 |
OUTCFG79
0x0 |
IRPTEN79
0x0 |
RDZERO79
0x0 |
INPEN79
0x0 |
FNCSEL79
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN79 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN79 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL79 | RW | Polarity select for NCE for GPIO 79 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC79 | RW | IOMSTR/MSPI N Chip Select 79, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG79 | RW | Pullup/Pulldown configuration for GPIO 79 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR79 | RW | Configure the slew rate |
| 11:10 | DS79 | RW | Drive strength selection for GPIO 79 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG79 | RW | Pin IO mode selection for GPIO pin 79 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN79 | RW | Interrupt enable for GPIO 79 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO79 | RW | Return 0 for read data on GPIO 79 |
| 4 | INPEN79 | RW | Input enable for GPIO 79 |
| 3:0 | FNCSEL79 | RW | Function select for GPIO pin 79 MSPI2_5 = 0x0 - MSPI Master 2 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. SDIF_DAT4 = 0x2 - SD/SDIO/MMC Data4 pin GPIO = 0x3 - General purpose I/O SWO = 0x4 - Serial Wire Output DISP_VS = 0x5 - Display RGB VSYNC CT79 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE79 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS15 = 0x8 - Observation bus bit 15 DISP_SPI_SDI = 0x9 - Display SPI Data IN RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010140 |
Controls the operation of GPIO pin 80.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN80
0x0 |
FIEN80
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL80
0x0 |
NCESRC80
0x0 |
PULLCFG80
0x0 |
SR80
0x0 |
DS80
0x0 |
OUTCFG80
0x0 |
IRPTEN80
0x0 |
RDZERO80
0x0 |
INPEN80
0x0 |
FNCSEL80
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN80 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN80 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL80 | RW | Polarity select for NCE for GPIO 80 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC80 | RW | IOMSTR/MSPI N Chip Select 80, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG80 | RW | Pullup/Pulldown configuration for GPIO 80 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR80 | RW | Configure the slew rate |
| 11:10 | DS80 | RW | Drive strength selection for GPIO 80 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG80 | RW | Pin IO mode selection for GPIO pin 80 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN80 | RW | Interrupt enable for GPIO 80 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO80 | RW | Return 0 for read data on GPIO 80 |
| 4 | INPEN80 | RW | Input enable for GPIO 80 |
| 3:0 | FNCSEL80 | RW | Function select for GPIO pin 80 MSPI2_6 = 0x0 - MSPI Master 2 Interface Signal CLKOUT = 0x1 - Oscillator output clock SDIF_DAT5 = 0x2 - SD/SDIO/MMC Data5 pin GPIO = 0x3 - General purpose I/O SWTRACE0 = 0x4 - Serial Wire Debug Trace Output 0 DISP_HS = 0x5 - Display RGB HSYNC CT80 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE80 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS0 = 0x8 - Observation bus bit 0 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010144 |
Controls the operation of GPIO pin 81.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN81
0x0 |
FIEN81
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL81
0x0 |
NCESRC81
0x0 |
PULLCFG81
0x0 |
SR81
0x0 |
DS81
0x0 |
OUTCFG81
0x0 |
IRPTEN81
0x0 |
RDZERO81
0x0 |
INPEN81
0x0 |
FNCSEL81
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN81 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN81 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL81 | RW | Polarity select for NCE for GPIO 81 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC81 | RW | IOMSTR/MSPI N Chip Select 81, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG81 | RW | Pullup/Pulldown configuration for GPIO 81 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR81 | RW | Configure the slew rate |
| 11:10 | DS81 | RW | Drive strength selection for GPIO 81 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG81 | RW | Pin IO mode selection for GPIO pin 81 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN81 | RW | Interrupt enable for GPIO 81 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO81 | RW | Return 0 for read data on GPIO 81 |
| 4 | INPEN81 | RW | Input enable for GPIO 81 |
| 3:0 | FNCSEL81 | RW | Function select for GPIO pin 81 MSPI2_7 = 0x0 - MSPI Master 2 Interface Signal CLKOUT = 0x1 - Oscillator output clock SDIF_DAT6 = 0x2 - SD/SDIO/MMC Data6 pin GPIO = 0x3 - General purpose I/O SWTRACE1 = 0x4 - Serial Wire Debug Trace Output 1 DISP_DE = 0x5 - Display RGB Data Enable CT81 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE81 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS1 = 0x8 - Observation bus bit 1 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010148 |
Controls the operation of GPIO pin 82.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN82
0x0 |
FIEN82
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL82
0x0 |
NCESRC82
0x0 |
PULLCFG82
0x0 |
SR82
0x0 |
DS82
0x0 |
OUTCFG82
0x0 |
IRPTEN82
0x0 |
RDZERO82
0x0 |
INPEN82
0x0 |
FNCSEL82
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN82 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN82 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL82 | RW | Polarity select for NCE for GPIO 82 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC82 | RW | IOMSTR/MSPI N Chip Select 82, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG82 | RW | Pullup/Pulldown configuration for GPIO 82 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR82 | RW | Configure the slew rate |
| 11:10 | DS82 | RW | Drive strength selection for GPIO 82 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG82 | RW | Pin IO mode selection for GPIO pin 82 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN82 | RW | Interrupt enable for GPIO 82 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO82 | RW | Return 0 for read data on GPIO 82 |
| 4 | INPEN82 | RW | Input enable for GPIO 82 |
| 3:0 | FNCSEL82 | RW | Function select for GPIO pin 82 MSPI2_8 = 0x0 - MSPI Master 2 Interface Signal 32KHzXT = 0x1 - 32kHZ from analog SDIF_DAT7 = 0x2 - SD/SDIO/MMC Data7 pin GPIO = 0x3 - General purpose I/O SWTRACE2 = 0x4 - Serial Wire Debug Trace Output 2 DISP_PCLK = 0x5 - Display RGB Pixel Clock CT82 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE82 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS2 = 0x8 - Observation bus bit 2 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001014C |
Controls the operation of GPIO pin 83.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN83
0x0 |
FIEN83
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL83
0x0 |
NCESRC83
0x0 |
PULLCFG83
0x0 |
SR83
0x0 |
DS83
0x0 |
OUTCFG83
0x0 |
IRPTEN83
0x0 |
RDZERO83
0x0 |
INPEN83
0x0 |
FNCSEL83
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN83 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN83 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL83 | RW | Polarity select for NCE for GPIO 83 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC83 | RW | IOMSTR/MSPI N Chip Select 83, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG83 | RW | Pullup/Pulldown configuration for GPIO 83 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR83 | RW | Configure the slew rate |
| 11:10 | DS83 | RW | Drive strength selection for GPIO 83 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG83 | RW | Pin IO mode selection for GPIO pin 83 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN83 | RW | Interrupt enable for GPIO 83 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO83 | RW | Return 0 for read data on GPIO 83 |
| 4 | INPEN83 | RW | Input enable for GPIO 83 |
| 3:0 | FNCSEL83 | RW | Function select for GPIO pin 83 MSPI2_9 = 0x0 - MSPI Master 2 Interface Signal 32KHzXT = 0x1 - 32kHZ from analog SDIF_CMD = 0x2 - SD1/SD4/MMC Command pin GPIO = 0x3 - General purpose I/O SWTRACE3 = 0x4 - Serial Wire Debug Trace Output 3 DISP_SD = 0x5 - Display RGB Shutdown CT83 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE83 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS3 = 0x8 - Observation bus bit 3 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010150 |
Controls the operation of GPIO pin 84.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN84
0x0 |
FIEN84
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL84
0x0 |
NCESRC84
0x0 |
PULLCFG84
0x0 |
SR84
0x0 |
DS84
0x0 |
OUTCFG84
0x0 |
IRPTEN84
0x0 |
RDZERO84
0x0 |
INPEN84
0x0 |
FNCSEL84
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN84 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN84 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL84 | RW | Polarity select for NCE for GPIO 84 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC84 | RW | IOMSTR/MSPI N Chip Select 84, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG84 | RW | Pullup/Pulldown configuration for GPIO 84 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR84 | RW | Configure the slew rate |
| 11:10 | DS84 | RW | Drive strength selection for GPIO 84 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG84 | RW | Pin IO mode selection for GPIO pin 84 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN84 | RW | Interrupt enable for GPIO 84 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO84 | RW | Return 0 for read data on GPIO 84 |
| 4 | INPEN84 | RW | Input enable for GPIO 84 |
| 3:0 | FNCSEL84 | RW | Function select for GPIO pin 84 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. SDIF_DAT0 = 0x2 - SD/SDIO/MMC Data0 pin GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT84 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE84 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS4 = 0x8 - Observation bus bit 4 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010154 |
Controls the operation of GPIO pin 85.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN85
0x0 |
FIEN85
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL85
0x0 |
NCESRC85
0x0 |
PULLCFG85
0x0 |
SR85
0x0 |
DS85
0x0 |
OUTCFG85
0x0 |
IRPTEN85
0x0 |
RDZERO85
0x0 |
INPEN85
0x0 |
FNCSEL85
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN85 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN85 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL85 | RW | Polarity select for NCE for GPIO 85 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC85 | RW | IOMSTR/MSPI N Chip Select 85, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG85 | RW | Pullup/Pulldown configuration for GPIO 85 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR85 | RW | Configure the slew rate |
| 11:10 | DS85 | RW | Drive strength selection for GPIO 85 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG85 | RW | Pin IO mode selection for GPIO pin 85 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN85 | RW | Interrupt enable for GPIO 85 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO85 | RW | Return 0 for read data on GPIO 85 |
| 4 | INPEN85 | RW | Input enable for GPIO 85 |
| 3:0 | FNCSEL85 | RW | Function select for GPIO pin 85 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. SDIF_DAT1 = 0x2 - SD/SDIO/MMC Data1 pin GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT85 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE85 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS5 = 0x8 - Observation bus bit 5 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010158 |
Controls the operation of GPIO pin 86.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN86
0x0 |
FIEN86
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL86
0x0 |
NCESRC86
0x0 |
PULLCFG86
0x0 |
SR86
0x0 |
DS86
0x0 |
OUTCFG86
0x0 |
IRPTEN86
0x0 |
RDZERO86
0x0 |
INPEN86
0x0 |
FNCSEL86
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN86 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN86 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL86 | RW | Polarity select for NCE for GPIO 86 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC86 | RW | IOMSTR/MSPI N Chip Select 86, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG86 | RW | Pullup/Pulldown configuration for GPIO 86 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR86 | RW | Configure the slew rate |
| 11:10 | DS86 | RW | Drive strength selection for GPIO 86 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG86 | RW | Pin IO mode selection for GPIO pin 86 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN86 | RW | Interrupt enable for GPIO 86 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO86 | RW | Return 0 for read data on GPIO 86 |
| 4 | INPEN86 | RW | Input enable for GPIO 86 |
| 3:0 | FNCSEL86 | RW | Function select for GPIO pin 86 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. SDIF_DAT2 = 0x2 - SD/SDIO/MMC Data2 pin GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT86 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE86 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS6 = 0x8 - Observation bus bit 6 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001015C |
Controls the operation of GPIO pin 87.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN87
0x0 |
FIEN87
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL87
0x0 |
NCESRC87
0x0 |
PULLCFG87
0x0 |
SR87
0x0 |
DS87
0x0 |
OUTCFG87
0x0 |
IRPTEN87
0x0 |
RDZERO87
0x0 |
INPEN87
0x0 |
FNCSEL87
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN87 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN87 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL87 | RW | Polarity select for NCE for GPIO 87 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC87 | RW | IOMSTR/MSPI N Chip Select 87, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG87 | RW | Pullup/Pulldown configuration for GPIO 87 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR87 | RW | Configure the slew rate |
| 11:10 | DS87 | RW | Drive strength selection for GPIO 87 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG87 | RW | Pin IO mode selection for GPIO pin 87 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN87 | RW | Interrupt enable for GPIO 87 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO87 | RW | Return 0 for read data on GPIO 87 |
| 4 | INPEN87 | RW | Input enable for GPIO 87 |
| 3:0 | FNCSEL87 | RW | Function select for GPIO pin 87 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. SDIF_DAT3 = 0x2 - SD/SDIO/MMC Data3 pin GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT87 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE87 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS7 = 0x8 - Observation bus bit 7 DISP_TE = 0x9 - Display TE input RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010160 |
Controls the operation of GPIO pin 88.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN88
0x0 |
FIEN88
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL88
0x0 |
NCESRC88
0x0 |
PULLCFG88
0x0 |
SR88
0x0 |
DS88
0x0 |
OUTCFG88
0x0 |
IRPTEN88
0x0 |
RDZERO88
0x0 |
INPEN88
0x0 |
FNCSEL88
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN88 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN88 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL88 | RW | Polarity select for NCE for GPIO 88 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC88 | RW | IOMSTR/MSPI N Chip Select 88, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG88 | RW | Pullup/Pulldown configuration for GPIO 88 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR88 | RW | Configure the slew rate |
| 11:10 | DS88 | RW | Drive strength selection for GPIO 88 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected 0P75X = 0x2 - 0.75x output driver selected 1P0X = 0x3 - 1.0x output driver selected |
| 9:8 | OUTCFG88 | RW | Pin IO mode selection for GPIO pin 88 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN88 | RW | Interrupt enable for GPIO 88 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO88 | RW | Return 0 for read data on GPIO 88 |
| 4 | INPEN88 | RW | Input enable for GPIO 88 |
| 3:0 | FNCSEL88 | RW | Function select for GPIO pin 88 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. SDIF_CLKOUT = 0x2 - SD/SDIO/MMC Clock to Card (CLK) GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT88 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE88 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS8 = 0x8 - Observation bus bit 8 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010164 |
Controls the operation of GPIO pin 89.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN89
0x0 |
FIEN89
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL89
0x0 |
NCESRC89
0x0 |
PULLCFG89
0x0 |
SR89
0x0 |
DS89
0x0 |
OUTCFG89
0x0 |
IRPTEN89
0x0 |
RDZERO89
0x0 |
INPEN89
0x0 |
FNCSEL89
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN89 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN89 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL89 | RW | Polarity select for NCE for GPIO 89 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC89 | RW | IOMSTR/MSPI N Chip Select 89, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG89 | RW | Pullup/Pulldown configuration for GPIO 89 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR89 | RW | Configure the slew rate |
| 11:10 | DS89 | RW | Drive strength selection for GPIO 89 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG89 | RW | Pin IO mode selection for GPIO pin 89 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN89 | RW | Interrupt enable for GPIO 89 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO89 | RW | Return 0 for read data on GPIO 89 |
| 4 | INPEN89 | RW | Input enable for GPIO 89 |
| 3:0 | FNCSEL89 | RW | Function select for GPIO pin 89 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. DISP_CM = 0x5 - Display RGB Color Mode CT89 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE89 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS9 = 0x8 - Observation bus bit 9 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010168 |
Controls the operation of GPIO pin 90.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN90
0x0 |
FIEN90
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL90
0x0 |
NCESRC90
0x0 |
PULLCFG90
0x0 |
SR90
0x0 |
DS90
0x0 |
OUTCFG90
0x0 |
IRPTEN90
0x0 |
RDZERO90
0x0 |
INPEN90
0x0 |
FNCSEL90
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN90 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN90 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL90 | RW | Polarity select for NCE for GPIO 90 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC90 | RW | IOMSTR/MSPI N Chip Select 90, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG90 | RW | Pullup/Pulldown configuration for GPIO 90 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR90 | RW | Configure the slew rate |
| 11:10 | DS90 | RW | Drive strength selection for GPIO 90 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG90 | RW | Pin IO mode selection for GPIO pin 90 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN90 | RW | Interrupt enable for GPIO 90 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO90 | RW | Return 0 for read data on GPIO 90 |
| 4 | INPEN90 | RW | Input enable for GPIO 90 |
| 3:0 | FNCSEL90 | RW | Function select for GPIO pin 90 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT90 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE90 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS10 = 0x8 - Observation bus bit 10 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001016C |
Controls the operation of GPIO pin 91.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN91
0x0 |
FIEN91
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL91
0x0 |
NCESRC91
0x0 |
PULLCFG91
0x0 |
SR91
0x0 |
DS91
0x0 |
OUTCFG91
0x0 |
IRPTEN91
0x0 |
RDZERO91
0x0 |
INPEN91
0x0 |
FNCSEL91
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN91 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN91 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL91 | RW | Polarity select for NCE for GPIO 91 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC91 | RW | IOMSTR/MSPI N Chip Select 91, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG91 | RW | Pullup/Pulldown configuration for GPIO 91 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR91 | RW | Configure the slew rate |
| 11:10 | DS91 | RW | Drive strength selection for GPIO 91 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG91 | RW | Pin IO mode selection for GPIO pin 91 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN91 | RW | Interrupt enable for GPIO 91 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO91 | RW | Return 0 for read data on GPIO 91 |
| 4 | INPEN91 | RW | Input enable for GPIO 91 |
| 3:0 | FNCSEL91 | RW | Function select for GPIO pin 91 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT91 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE91 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS11 = 0x8 - Observation bus bit 11 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010170 |
Controls the operation of GPIO pin 92.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN92
0x0 |
FIEN92
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL92
0x0 |
NCESRC92
0x0 |
PULLCFG92
0x0 |
SR92
0x0 |
DS92
0x0 |
OUTCFG92
0x0 |
IRPTEN92
0x0 |
RDZERO92
0x0 |
INPEN92
0x0 |
FNCSEL92
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN92 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN92 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL92 | RW | Polarity select for NCE for GPIO 92 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC92 | RW | IOMSTR/MSPI N Chip Select 92, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG92 | RW | Pullup/Pulldown configuration for GPIO 92 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR92 | RW | Configure the slew rate |
| 11:10 | DS92 | RW | Drive strength selection for GPIO 92 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG92 | RW | Pin IO mode selection for GPIO pin 92 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN92 | RW | Interrupt enable for GPIO 92 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO92 | RW | Return 0 for read data on GPIO 92 |
| 4 | INPEN92 | RW | Input enable for GPIO 92 |
| 3:0 | FNCSEL92 | RW | Function select for GPIO pin 92 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT92 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE92 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS12 = 0x8 - Observation bus bit 12 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010174 |
Controls the operation of GPIO pin 93.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN93
0x0 |
FIEN93
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL93
0x0 |
NCESRC93
0x0 |
PULLCFG93
0x0 |
SR93
0x0 |
DS93
0x0 |
OUTCFG93
0x0 |
IRPTEN93
0x0 |
RDZERO93
0x0 |
INPEN93
0x0 |
FNCSEL93
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN93 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN93 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL93 | RW | Polarity select for NCE for GPIO 93 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC93 | RW | IOMSTR/MSPI N Chip Select 93, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG93 | RW | Pullup/Pulldown configuration for GPIO 93 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR93 | RW | Configure the slew rate |
| 11:10 | DS93 | RW | Drive strength selection for GPIO 93 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG93 | RW | Pin IO mode selection for GPIO pin 93 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN93 | RW | Interrupt enable for GPIO 93 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO93 | RW | Return 0 for read data on GPIO 93 |
| 4 | INPEN93 | RW | Input enable for GPIO 93 |
| 3:0 | FNCSEL93 | RW | Function select for GPIO pin 93 MSPI2_9 = 0x0 - MSPI Master 2 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT93 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE93 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS13 = 0x8 - Observation bus bit 13 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010178 |
Controls the operation of GPIO pin 94.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN94
0x0 |
FIEN94
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL94
0x0 |
NCESRC94
0x0 |
PULLCFG94
0x0 |
SR94
0x0 |
DS94
0x0 |
OUTCFG94
0x0 |
IRPTEN94
0x0 |
RDZERO94
0x0 |
INPEN94
0x0 |
FNCSEL94
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN94 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN94 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL94 | RW | Polarity select for NCE for GPIO 94 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC94 | RW | IOMSTR/MSPI N Chip Select 94, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG94 | RW | Pullup/Pulldown configuration for GPIO 94 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR94 | RW | Configure the slew rate |
| 11:10 | DS94 | RW | Drive strength selection for GPIO 94 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG94 | RW | Pin IO mode selection for GPIO pin 94 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN94 | RW | Interrupt enable for GPIO 94 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO94 | RW | Return 0 for read data on GPIO 94 |
| 4 | INPEN94 | RW | Input enable for GPIO 94 |
| 3:0 | FNCSEL94 | RW | Function select for GPIO pin 94 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT94 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE94 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS14 = 0x8 - Observation bus bit 14 VCMPO = 0x9 - Output of the voltage comparator signal RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001017C |
Controls the operation of GPIO pin 95.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN95
0x0 |
FIEN95
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL95
0x0 |
NCESRC95
0x0 |
PULLCFG95
0x0 |
SR95
0x0 |
DS95
0x0 |
OUTCFG95
0x0 |
IRPTEN95
0x0 |
RDZERO95
0x0 |
INPEN95
0x0 |
FNCSEL95
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN95 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN95 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL95 | RW | Polarity select for NCE for GPIO 95 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC95 | RW | IOMSTR/MSPI N Chip Select 95, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG95 | RW | Pullup/Pulldown configuration for GPIO 95 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR95 | RW | Configure the slew rate |
| 11:10 | DS95 | RW | Drive strength selection for GPIO 95 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG95 | RW | Pin IO mode selection for GPIO pin 95 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN95 | RW | Interrupt enable for GPIO 95 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO95 | RW | Return 0 for read data on GPIO 95 |
| 4 | INPEN95 | RW | Input enable for GPIO 95 |
| 3:0 | FNCSEL95 | RW | Function select for GPIO pin 95 MSPI1_0 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT95 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE95 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS15 = 0x8 - Observation bus bit 15 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010180 |
Controls the operation of GPIO pin 96.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN96
0x0 |
FIEN96
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL96
0x0 |
NCESRC96
0x0 |
PULLCFG96
0x0 |
SR96
0x0 |
DS96
0x0 |
OUTCFG96
0x0 |
IRPTEN96
0x0 |
RDZERO96
0x0 |
INPEN96
0x0 |
FNCSEL96
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN96 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN96 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL96 | RW | Polarity select for NCE for GPIO 96 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC96 | RW | IOMSTR/MSPI N Chip Select 96, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG96 | RW | Pullup/Pulldown configuration for GPIO 96 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR96 | RW | Configure the slew rate |
| 11:10 | DS96 | RW | Drive strength selection for GPIO 96 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG96 | RW | Pin IO mode selection for GPIO pin 96 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN96 | RW | Interrupt enable for GPIO 96 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO96 | RW | Return 0 for read data on GPIO 96 |
| 4 | INPEN96 | RW | Input enable for GPIO 96 |
| 3:0 | FNCSEL96 | RW | Function select for GPIO pin 96 MSPI1_1 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT96 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE96 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS0 = 0x8 - Observation bus bit 0 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010184 |
Controls the operation of GPIO pin 97.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN97
0x0 |
FIEN97
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL97
0x0 |
NCESRC97
0x0 |
PULLCFG97
0x0 |
SR97
0x0 |
DS97
0x0 |
OUTCFG97
0x0 |
IRPTEN97
0x0 |
RDZERO97
0x0 |
INPEN97
0x0 |
FNCSEL97
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN97 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN97 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL97 | RW | Polarity select for NCE for GPIO 97 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC97 | RW | IOMSTR/MSPI N Chip Select 97, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG97 | RW | Pullup/Pulldown configuration for GPIO 97 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR97 | RW | Configure the slew rate |
| 11:10 | DS97 | RW | Drive strength selection for GPIO 97 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG97 | RW | Pin IO mode selection for GPIO pin 97 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN97 | RW | Interrupt enable for GPIO 97 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO97 | RW | Return 0 for read data on GPIO 97 |
| 4 | INPEN97 | RW | Input enable for GPIO 97 |
| 3:0 | FNCSEL97 | RW | Function select for GPIO pin 97 MSPI1_2 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT97 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE97 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS1 = 0x8 - Observation bus bit 1 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010188 |
Controls the operation of GPIO pin 98.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN98
0x0 |
FIEN98
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL98
0x0 |
NCESRC98
0x0 |
PULLCFG98
0x0 |
SR98
0x0 |
DS98
0x0 |
OUTCFG98
0x0 |
IRPTEN98
0x0 |
RDZERO98
0x0 |
INPEN98
0x0 |
FNCSEL98
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN98 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN98 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL98 | RW | Polarity select for NCE for GPIO 98 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC98 | RW | IOMSTR/MSPI N Chip Select 98, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG98 | RW | Pullup/Pulldown configuration for GPIO 98 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR98 | RW | Configure the slew rate |
| 11:10 | DS98 | RW | Drive strength selection for GPIO 98 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG98 | RW | Pin IO mode selection for GPIO pin 98 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN98 | RW | Interrupt enable for GPIO 98 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO98 | RW | Return 0 for read data on GPIO 98 |
| 4 | INPEN98 | RW | Input enable for GPIO 98 |
| 3:0 | FNCSEL98 | RW | Function select for GPIO pin 98 MSPI1_3 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT98 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE98 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS2 = 0x8 - Observation bus bit 2 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001018C |
Controls the operation of GPIO pin 99.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN99
0x0 |
FIEN99
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL99
0x0 |
NCESRC99
0x0 |
PULLCFG99
0x0 |
SR99
0x0 |
DS99
0x0 |
OUTCFG99
0x0 |
IRPTEN99
0x0 |
RDZERO99
0x0 |
INPEN99
0x0 |
FNCSEL99
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN99 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN99 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL99 | RW | Polarity select for NCE for GPIO 99 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC99 | RW | IOMSTR/MSPI N Chip Select 99, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG99 | RW | Pullup/Pulldown configuration for GPIO 99 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR99 | RW | Configure the slew rate |
| 11:10 | DS99 | RW | Drive strength selection for GPIO 99 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG99 | RW | Pin IO mode selection for GPIO pin 99 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN99 | RW | Interrupt enable for GPIO 99 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO99 | RW | Return 0 for read data on GPIO 99 |
| 4 | INPEN99 | RW | Input enable for GPIO 99 |
| 3:0 | FNCSEL99 | RW | Function select for GPIO pin 99 MSPI1_4 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT99 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE99 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS3 = 0x8 - Observation bus bit 3 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010190 |
Controls the operation of GPIO pin 100.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN100
0x0 |
FIEN100
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL100
0x0 |
NCESRC100
0x0 |
PULLCFG100
0x0 |
SR100
0x0 |
DS100
0x0 |
OUTCFG100
0x0 |
IRPTEN100
0x0 |
RDZERO100
0x0 |
INPEN100
0x0 |
FNCSEL100
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN100 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN100 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL100 | RW | Polarity select for NCE for GPIO 100 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC100 | RW | IOMSTR/MSPI N Chip Select 100, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG100 | RW | Pullup/Pulldown configuration for GPIO 100 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR100 | RW | Configure the slew rate |
| 11:10 | DS100 | RW | Drive strength selection for GPIO 100 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG100 | RW | Pin IO mode selection for GPIO pin 100 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN100 | RW | Interrupt enable for GPIO 100 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO100 | RW | Return 0 for read data on GPIO 100 |
| 4 | INPEN100 | RW | Input enable for GPIO 100 |
| 3:0 | FNCSEL100 | RW | Function select for GPIO pin 100 MSPI1_5 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT100 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE100 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS4 = 0x8 - Observation bus bit 4 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010194 |
Controls the operation of GPIO pin 101.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN101
0x0 |
FIEN101
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL101
0x0 |
NCESRC101
0x0 |
PULLCFG101
0x0 |
SR101
0x0 |
DS101
0x0 |
OUTCFG101
0x0 |
IRPTEN101
0x0 |
RDZERO101
0x0 |
INPEN101
0x0 |
FNCSEL101
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN101 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN101 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL101 | RW | Polarity select for NCE for GPIO 101 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC101 | RW | IOMSTR/MSPI N Chip Select 101, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG101 | RW | Pullup/Pulldown configuration for GPIO 101 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR101 | RW | Configure the slew rate |
| 11:10 | DS101 | RW | Drive strength selection for GPIO 101 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG101 | RW | Pin IO mode selection for GPIO pin 101 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN101 | RW | Interrupt enable for GPIO 101 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO101 | RW | Return 0 for read data on GPIO 101 |
| 4 | INPEN101 | RW | Input enable for GPIO 101 |
| 3:0 | FNCSEL101 | RW | Function select for GPIO pin 101 MSPI1_6 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT101 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE101 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS5 = 0x8 - Observation bus bit 5 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010198 |
Controls the operation of GPIO pin 102.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN102
0x0 |
FIEN102
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL102
0x0 |
NCESRC102
0x0 |
PULLCFG102
0x0 |
SR102
0x0 |
DS102
0x0 |
OUTCFG102
0x0 |
IRPTEN102
0x0 |
RDZERO102
0x0 |
INPEN102
0x0 |
FNCSEL102
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN102 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN102 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL102 | RW | Polarity select for NCE for GPIO 102 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC102 | RW | IOMSTR/MSPI N Chip Select 102, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG102 | RW | Pullup/Pulldown configuration for GPIO 102 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR102 | RW | Configure the slew rate |
| 11:10 | DS102 | RW | Drive strength selection for GPIO 102 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG102 | RW | Pin IO mode selection for GPIO pin 102 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN102 | RW | Interrupt enable for GPIO 102 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO102 | RW | Return 0 for read data on GPIO 102 |
| 4 | INPEN102 | RW | Input enable for GPIO 102 |
| 3:0 | FNCSEL102 | RW | Function select for GPIO pin 102 MSPI1_7 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT102 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE102 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS6 = 0x8 - Observation bus bit 6 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x4001019C |
Controls the operation of GPIO pin 103.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN103
0x0 |
FIEN103
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL103
0x0 |
NCESRC103
0x0 |
PULLCFG103
0x0 |
SR103
0x0 |
DS103
0x0 |
OUTCFG103
0x0 |
IRPTEN103
0x0 |
RDZERO103
0x0 |
INPEN103
0x0 |
FNCSEL103
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN103 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN103 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL103 | RW | Polarity select for NCE for GPIO 103 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC103 | RW | IOMSTR/MSPI N Chip Select 103, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG103 | RW | Pullup/Pulldown configuration for GPIO 103 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR103 | RW | Configure the slew rate |
| 11:10 | DS103 | RW | Drive strength selection for GPIO 103 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG103 | RW | Pin IO mode selection for GPIO pin 103 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN103 | RW | Interrupt enable for GPIO 103 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO103 | RW | Return 0 for read data on GPIO 103 |
| 4 | INPEN103 | RW | Input enable for GPIO 103 |
| 3:0 | FNCSEL103 | RW | Function select for GPIO pin 103 MSPI1_8 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT103 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE103 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS7 = 0x8 - Observation bus bit 7 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101A0 |
Controls the operation of GPIO pin 104.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED27
0x0 |
FOEN104
0x0 |
FIEN104
0x0 |
RESERVED11
0x0 |
RESERVED23
0x0 |
NCEPOL104
0x0 |
NCESRC104
0x0 |
PULLCFG104
0x0 |
SR104
0x0 |
DS104
0x0 |
OUTCFG104
0x0 |
IRPTEN104
0x0 |
RDZERO104
0x0 |
INPEN104
0x0 |
FNCSEL104
0x3 |
|||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RESERVED27 | RW | Reserved |
| 27 | FOEN104 | RW | Force output enable active regardless of function selected. Otherwise the selected function will enable the output only when needed |
| 26 | FIEN104 | RW | Force input enable active regardless of function selected. Otherwise the selected function will enable the input only when needed |
| 25 | RESERVED11 | RW | Reserved |
| 24:23 | RESERVED23 | RW | Reserved |
| 22 | NCEPOL104 | RW | Polarity select for NCE for GPIO 104 LOW = 0x0 - Polarity is active low HIGH = 0x1 - Polarity is active high |
| 21:16 | NCESRC104 | RW | IOMSTR/MSPI N Chip Select 104, DISP control signals DE, CSX, and CS. Polarity is determined by CE_POLARITY field IOM0CE0 = 0x0 - IOM 0 NCE 0 module IOM0CE1 = 0x1 - IOM 0 NCE 1 module IOM0CE2 = 0x2 - IOM 0 NCE 2 module IOM0CE3 = 0x3 - IOM 0 NCE 3 module IOM1CE0 = 0x4 - IOM 1 NCE 0 module IOM1CE1 = 0x5 - IOM 1 NCE 1 module IOM1CE2 = 0x6 - IOM 1 NCE 2 module IOM1CE3 = 0x7 - IOM 1 NCE 3 module IOM2CE0 = 0x8 - IOM 2 NCE 0 module IOM2CE1 = 0x9 - IOM 2 NCE 1 module IOM2CE2 = 0xA - IOM 2 NCE 2 module IOM2CE3 = 0xB - IOM 2 NCE 3 module IOM3CE0 = 0xC - IOM 3 NCE 0 module IOM3CE1 = 0xD - IOM 3 NCE 1 module IOM3CE2 = 0xE - IOM 3 NCE 2 module IOM3CE3 = 0xF - IOM 3 NCE 3 module IOM4CE0 = 0x10 - IOM 4 NCE 0 module IOM4CE1 = 0x11 - IOM 4 NCE 1 module IOM4CE2 = 0x12 - IOM 4 NCE 2 module IOM4CE3 = 0x13 - IOM 4 NCE 3 module IOM5CE0 = 0x14 - IOM 5 NCE 0 module IOM5CE1 = 0x15 - IOM 5 NCE 1 module IOM5CE2 = 0x16 - IOM 5 NCE 2 module IOM5CE3 = 0x17 - IOM 5 NCE 3 module IOM6CE0 = 0x18 - IOM 6 NCE 0 module IOM6CE1 = 0x19 - IOM 6 NCE 1 module IOM6CE2 = 0x1A - IOM 6 NCE 2 module IOM6CE3 = 0x1B - IOM 6 NCE 3 module IOM7CE0 = 0x1C - IOM 7 NCE 0 module IOM7CE1 = 0x1D - IOM 7 NCE 1 module IOM7CE2 = 0x1E - IOM 7 NCE 2 module IOM7CE3 = 0x1F - IOM 7 NCE 3 module MSPI0CEN0 = 0x20 - MSPI 0 NCE 0 module MSPI0CEN1 = 0x21 - MSPI 0 NCE 1 module MSPI1CEN0 = 0x22 - MSPI 1 NCE 0 module MSPI1CEN1 = 0x23 - MSPI 1 NCE 1 module MSPI2CEN0 = 0x24 - MSPI 2 NCE 0 module MSPI2CEN1 = 0x25 - MSPI 2 NCE 1 module DC_DPI_DE = 0x26 - DC DPI DE module DISP_CONT_CSX = 0x27 - DISP CONT CSX module DC_SPI_CS_N = 0x28 - DC SPI CS_N module DC_QSPI_CS_N = 0x29 - DC QSPI CS_N module DC_RESX = 0x2A - DC module RESX |
| 15:13 | PULLCFG104 | RW | Pullup/Pulldown configuration for GPIO 104 DIS = 0x0 - No pullup or pulldown selected PD50K = 0x1 - 50K Pulldown selected PU15K = 0x2 - 1.5K Pullup selected PU6K = 0x3 - 6K Pullup selected PU12K = 0x4 - 12K Pullup selected PU24K = 0x5 - 24K Pullup selected PU50K = 0x6 - 50K Pullup selected PU100K = 0x7 - 100K Pullup selected |
| 12 | SR104 | RW | Configure the slew rate |
| 11:10 | DS104 | RW | Drive strength selection for GPIO 104 0P1X = 0x0 - 0.1x output driver selected 0P5X = 0x1 - 0.5x output driver selected |
| 9:8 | OUTCFG104 | RW | Pin IO mode selection for GPIO pin 104 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN104 | RW | Interrupt enable for GPIO 104 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO104 | RW | Return 0 for read data on GPIO 104 |
| 4 | INPEN104 | RW | Input enable for GPIO 104 |
| 3:0 | FNCSEL104 | RW | Function select for GPIO pin 104 MSPI1_9 = 0x0 - MSPI Master 1 Interface Signal RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT104 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. NCE104 = 0x7 - IOMSTR/MSPI N Chip Select. Polarity is determined by CE_POLARITY field OBSBUS8 = 0x8 - Observation bus bit 8 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. FPIO = 0xB - Fast PIO RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101A4 |
Controls the operation of virtual GPIO pin 105.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG105
0x0 |
IRPTEN105
0x0 |
RDZERO105
0x0 |
INPEN105
0x0 |
FNCSEL105
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG105 | RW | Pin IO mode selection for GPIO pin 105 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN105 | RW | Interrupt enable for GPIO 105 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO105 | RW | Return 0 for read data on GPIO 105 |
| 4 | INPEN105 | RW | Input enable for GPIO 105 |
| 3:0 | FNCSEL105 | RW | Function select for GPIO pin 105 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT105 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS9 = 0x8 - Observation bus bit 9 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101A8 |
Controls the operation of virtual GPIO pin 106.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG106
0x0 |
IRPTEN106
0x0 |
RDZERO106
0x0 |
INPEN106
0x0 |
FNCSEL106
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG106 | RW | Pin IO mode selection for GPIO pin 106 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN106 | RW | Interrupt enable for GPIO 106 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO106 | RW | Return 0 for read data on GPIO 106 |
| 4 | INPEN106 | RW | Input enable for GPIO 106 |
| 3:0 | FNCSEL106 | RW | Function select for GPIO pin 106 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT106 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS10 = 0x8 - Observation bus bit 10 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101AC |
Controls the operation of virtual GPIO pin 107.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG107
0x0 |
IRPTEN107
0x0 |
RDZERO107
0x0 |
INPEN107
0x0 |
FNCSEL107
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG107 | RW | Pin IO mode selection for GPIO pin 107 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN107 | RW | Interrupt enable for GPIO 107 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO107 | RW | Return 0 for read data on GPIO 107 |
| 4 | INPEN107 | RW | Input enable for GPIO 107 |
| 3:0 | FNCSEL107 | RW | Function select for GPIO pin 107 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT107 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS11 = 0x8 - Observation bus bit 11 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101B0 |
Controls the operation of virtual GPIO pin 108.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG108
0x0 |
IRPTEN108
0x0 |
RDZERO108
0x0 |
INPEN108
0x0 |
FNCSEL108
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG108 | RW | Pin IO mode selection for GPIO pin 108 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN108 | RW | Interrupt enable for GPIO 108 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO108 | RW | Return 0 for read data on GPIO 108 |
| 4 | INPEN108 | RW | Input enable for GPIO 108 |
| 3:0 | FNCSEL108 | RW | Function select for GPIO pin 108 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT108 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS12 = 0x8 - Observation bus bit 12 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101B4 |
Controls the operation of virtual GPIO pin 109.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG109
0x0 |
IRPTEN109
0x0 |
RDZERO109
0x0 |
INPEN109
0x0 |
FNCSEL109
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG109 | RW | Pin IO mode selection for GPIO pin 109 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN109 | RW | Interrupt enable for GPIO 109 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO109 | RW | Return 0 for read data on GPIO 109 |
| 4 | INPEN109 | RW | Input enable for GPIO 109 |
| 3:0 | FNCSEL109 | RW | Function select for GPIO pin 109 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT109 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS13 = 0x8 - Observation bus bit 13 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101B8 |
Controls the operation of virtual GPIO pin 110.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG110
0x0 |
IRPTEN110
0x0 |
RDZERO110
0x0 |
INPEN110
0x0 |
FNCSEL110
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG110 | RW | Pin IO mode selection for GPIO pin 110 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN110 | RW | Interrupt enable for GPIO 110 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO110 | RW | Return 0 for read data on GPIO 110 |
| 4 | INPEN110 | RW | Input enable for GPIO 110 |
| 3:0 | FNCSEL110 | RW | Function select for GPIO pin 110 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT110 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS14 = 0x8 - Observation bus bit 14 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101BC |
Controls the operation of virtual GPIO pin 111.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG111
0x0 |
IRPTEN111
0x0 |
RDZERO111
0x0 |
INPEN111
0x0 |
FNCSEL111
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG111 | RW | Pin IO mode selection for GPIO pin 111 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN111 | RW | Interrupt enable for GPIO 111 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO111 | RW | Return 0 for read data on GPIO 111 |
| 4 | INPEN111 | RW | Input enable for GPIO 111 |
| 3:0 | FNCSEL111 | RW | Function select for GPIO pin 111 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT111 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS15 = 0x8 - Observation bus bit 15 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101C0 |
Controls the operation of virtual GPIO pin 112.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG112
0x0 |
IRPTEN112
0x0 |
RDZERO112
0x0 |
INPEN112
0x0 |
FNCSEL112
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG112 | RW | Pin IO mode selection for GPIO pin 112 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN112 | RW | Interrupt enable for GPIO 112 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO112 | RW | Return 0 for read data on GPIO 112 |
| 4 | INPEN112 | RW | Input enable for GPIO 112 |
| 3:0 | FNCSEL112 | RW | Function select for GPIO pin 112 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT112 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS0 = 0x8 - Observation bus bit 0 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101C4 |
Controls the operation of virtual GPIO pin 113.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG113
0x0 |
IRPTEN113
0x0 |
RDZERO113
0x0 |
INPEN113
0x0 |
FNCSEL113
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG113 | RW | Pin IO mode selection for GPIO pin 113 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN113 | RW | Interrupt enable for GPIO 113 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO113 | RW | Return 0 for read data on GPIO 113 |
| 4 | INPEN113 | RW | Input enable for GPIO 113 |
| 3:0 | FNCSEL113 | RW | Function select for GPIO pin 113 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT113 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS1 = 0x8 - Observation bus bit 1 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101C8 |
Controls the operation of virtual GPIO pin 114.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG114
0x0 |
IRPTEN114
0x0 |
RDZERO114
0x0 |
INPEN114
0x0 |
FNCSEL114
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG114 | RW | Pin IO mode selection for GPIO pin 114 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN114 | RW | Interrupt enable for GPIO 114 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO114 | RW | Return 0 for read data on GPIO 114 |
| 4 | INPEN114 | RW | Input enable for GPIO 114 |
| 3:0 | FNCSEL114 | RW | Function select for GPIO pin 114 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT114 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS2 = 0x8 - Observation bus bit 2 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101CC |
Controls the operation of virtual GPIO pin 115.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG115
0x0 |
IRPTEN115
0x0 |
RDZERO115
0x0 |
INPEN115
0x0 |
FNCSEL115
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG115 | RW | Pin IO mode selection for GPIO pin 115 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN115 | RW | Interrupt enable for GPIO 115 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO115 | RW | Return 0 for read data on GPIO 115 |
| 4 | INPEN115 | RW | Input enable for GPIO 115 |
| 3:0 | FNCSEL115 | RW | Function select for GPIO pin 115 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT115 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS3 = 0x8 - Observation bus bit 3 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101D0 |
Controls the operation of virtual GPIO pin 116.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG116
0x0 |
IRPTEN116
0x0 |
RDZERO116
0x0 |
INPEN116
0x0 |
FNCSEL116
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG116 | RW | Pin IO mode selection for GPIO pin 116 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN116 | RW | Interrupt enable for GPIO 116 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO116 | RW | Return 0 for read data on GPIO 116 |
| 4 | INPEN116 | RW | Input enable for GPIO 116 |
| 3:0 | FNCSEL116 | RW | Function select for GPIO pin 116 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT116 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS4 = 0x8 - Observation bus bit 4 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101D4 |
Controls the operation of virtual GPIO pin 117.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG117
0x0 |
IRPTEN117
0x0 |
RDZERO117
0x0 |
INPEN117
0x0 |
FNCSEL117
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG117 | RW | Pin IO mode selection for GPIO pin 117 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN117 | RW | Interrupt enable for GPIO 117 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO117 | RW | Return 0 for read data on GPIO 117 |
| 4 | INPEN117 | RW | Input enable for GPIO 117 |
| 3:0 | FNCSEL117 | RW | Function select for GPIO pin 117 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT117 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS5 = 0x8 - Observation bus bit 5 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101D8 |
Controls the operation of virtual GPIO pin 118.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG118
0x0 |
IRPTEN118
0x0 |
RDZERO118
0x0 |
INPEN118
0x0 |
FNCSEL118
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG118 | RW | Pin IO mode selection for GPIO pin 118 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN118 | RW | Interrupt enable for GPIO 118 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO118 | RW | Return 0 for read data on GPIO 118 |
| 4 | INPEN118 | RW | Input enable for GPIO 118 |
| 3:0 | FNCSEL118 | RW | Function select for GPIO pin 118 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT118 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS6 = 0x8 - Observation bus bit 6 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101DC |
Controls the operation of virtual GPIO pin 119.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG119
0x0 |
IRPTEN119
0x0 |
RDZERO119
0x0 |
INPEN119
0x0 |
FNCSEL119
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG119 | RW | Pin IO mode selection for GPIO pin 119 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN119 | RW | Interrupt enable for GPIO 119 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO119 | RW | Return 0 for read data on GPIO 119 |
| 4 | INPEN119 | RW | Input enable for GPIO 119 |
| 3:0 | FNCSEL119 | RW | Function select for GPIO pin 119 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT119 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS7 = 0x8 - Observation bus bit 7 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101E0 |
Controls the operation of virtual GPIO pin 120.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG120
0x0 |
IRPTEN120
0x0 |
RDZERO120
0x0 |
INPEN120
0x0 |
FNCSEL120
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG120 | RW | Pin IO mode selection for GPIO pin 120 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN120 | RW | Interrupt enable for GPIO 120 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO120 | RW | Return 0 for read data on GPIO 120 |
| 4 | INPEN120 | RW | Input enable for GPIO 120 |
| 3:0 | FNCSEL120 | RW | Function select for GPIO pin 120 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT120 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS8 = 0x8 - Observation bus bit 8 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101E4 |
Controls the operation of virtual GPIO pin 121.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG121
0x0 |
IRPTEN121
0x0 |
RDZERO121
0x0 |
INPEN121
0x0 |
FNCSEL121
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG121 | RW | Pin IO mode selection for GPIO pin 121 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN121 | RW | Interrupt enable for GPIO 121 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO121 | RW | Return 0 for read data on GPIO 121 |
| 4 | INPEN121 | RW | Input enable for GPIO 121 |
| 3:0 | FNCSEL121 | RW | Function select for GPIO pin 121 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT121 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS9 = 0x8 - Observation bus bit 9 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101E8 |
Controls the operation of virtual GPIO pin 122.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG122
0x0 |
IRPTEN122
0x0 |
RDZERO122
0x0 |
INPEN122
0x0 |
FNCSEL122
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG122 | RW | Pin IO mode selection for GPIO pin 122 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN122 | RW | Interrupt enable for GPIO 122 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO122 | RW | Return 0 for read data on GPIO 122 |
| 4 | INPEN122 | RW | Input enable for GPIO 122 |
| 3:0 | FNCSEL122 | RW | Function select for GPIO pin 122 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT122 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS10 = 0x8 - Observation bus bit 10 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101EC |
Controls the operation of virtual GPIO pin 123.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG123
0x0 |
IRPTEN123
0x0 |
RDZERO123
0x0 |
INPEN123
0x0 |
FNCSEL123
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG123 | RW | Pin IO mode selection for GPIO pin 123 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN123 | RW | Interrupt enable for GPIO 123 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO123 | RW | Return 0 for read data on GPIO 123 |
| 4 | INPEN123 | RW | Input enable for GPIO 123 |
| 3:0 | FNCSEL123 | RW | Function select for GPIO pin 123 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT123 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS11 = 0x8 - Observation bus bit 11 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101F0 |
Controls the operation of virtual GPIO pin 124.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG124
0x0 |
IRPTEN124
0x0 |
RDZERO124
0x0 |
INPEN124
0x0 |
FNCSEL124
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG124 | RW | Pin IO mode selection for GPIO pin 124 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN124 | RW | Interrupt enable for GPIO 124 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO124 | RW | Return 0 for read data on GPIO 124 |
| 4 | INPEN124 | RW | Input enable for GPIO 124 |
| 3:0 | FNCSEL124 | RW | Function select for GPIO pin 124 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT124 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS12 = 0x8 - Observation bus bit 12 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101F4 |
Controls the operation of virtual GPIO pin 125.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG125
0x0 |
IRPTEN125
0x0 |
RDZERO125
0x0 |
INPEN125
0x0 |
FNCSEL125
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG125 | RW | Pin IO mode selection for GPIO pin 125 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN125 | RW | Interrupt enable for GPIO 125 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO125 | RW | Return 0 for read data on GPIO 125 |
| 4 | INPEN125 | RW | Input enable for GPIO 125 |
| 3:0 | FNCSEL125 | RW | Function select for GPIO pin 125 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT125 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS13 = 0x8 - Observation bus bit 13 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101F8 |
Controls the operation of virtual GPIO pin 126.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG126
0x0 |
IRPTEN126
0x0 |
RDZERO126
0x0 |
INPEN126
0x0 |
FNCSEL126
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG126 | RW | Pin IO mode selection for GPIO pin 126 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN126 | RW | Interrupt enable for GPIO 126 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO126 | RW | Return 0 for read data on GPIO 126 |
| 4 | INPEN126 | RW | Input enable for GPIO 126 |
| 3:0 | FNCSEL126 | RW | Function select for GPIO pin 126 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT126 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS14 = 0x8 - Observation bus bit 14 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x400101FC |
Controls the operation of virtual GPIO pin 127.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RESERVED10
0x0 |
OUTCFG127
0x0 |
IRPTEN127
0x0 |
RDZERO127
0x0 |
INPEN127
0x0 |
FNCSEL127
0x3 |
||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RESERVED10 | RO | Reserved |
| 9:8 | OUTCFG127 | RW | Pin IO mode selection for GPIO pin 127 DIS = 0x0 - Output Disabled PUSHPULL = 0x1 - Output configured in push pull mode. Will drive 0 and 1 values on pin. OD = 0x2 - Output configured in open drain mode. Will only drive pin low, tristate otherwise. TS = 0x3 - Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. |
| 7:6 | IRPTEN127 | RW | Interrupt enable for GPIO 127 DIS = 0x0 - Interrupts are disabled for this GPIO INTFALL = 0x1 - Interrupts are enabled for falling edge transition on this GPIO INTRISE = 0x2 - Interrupts are enabled for rising edge transitions on this GPIO INTANY = 0x3 - Interrupts are enabled for any edge transition on this GPIO |
| 5 | RDZERO127 | RW | Return 0 for read data on GPIO 127 |
| 4 | INPEN127 | RW | Input enable for GPIO 127 |
| 3:0 | FNCSEL127 | RW | Function select for GPIO pin 127 RESERVED0 = 0x0 - Reserved selection. Operation unknown if selected. RESERVED1 = 0x1 - Reserved selection. Operation unknown if selected. RESERVED2 = 0x2 - Reserved selection. Operation unknown if selected. GPIO = 0x3 - General purpose I/O RESERVED4 = 0x4 - Reserved selection. Operation unknown if selected. RESERVED5 = 0x5 - Reserved selection. Operation unknown if selected. CT127 = 0x6 - Timer/Counter input or output; Selection of direction is done via CTIMER register settings. RESERVED7 = 0x7 - Reserved selection. Operation unknown if selected. OBSBUS15 = 0x8 - Observation bus bit 15 RESERVED9 = 0x9 - Reserved selection. Operation unknown if selected. RESERVED10 = 0xA - Reserved selection. Operation unknown if selected. RESERVED11 = 0xB - Reserved selection. Operation unknown if selected. RESERVED12 = 0xC - Reserved selection. Operation unknown if selected. RESERVED13 = 0xD - Reserved selection. Operation unknown if selected. RESERVED14 = 0xE - Reserved selection. Operation unknown if selected. RESERVED15 = 0xF - Reserved selection. Operation unknown if selected. |
| Instance 0 Address: | 0x40010200 |
Lock state of the PINCFG and GPIO configuration registers. Write a value of 0x73 to unlock write access to the PAD and GPIO.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PADKEY
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | PADKEY | RW | Key register value. Key = 0x73 - Key value to unlock the register. |
| Instance 0 Address: | 0x40010204 |
GPIO Input 0 (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RD0
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | RD0 | RO | GPIO31-0 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive. |
| Instance 0 Address: | 0x40010208 |
GPIO Input 1 (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RD1
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | RD1 | RO | GPIO63-32 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive. |
| Instance 0 Address: | 0x4001020C |
GPIO Input 2 (95-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RD2
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | RD2 | RO | GPIO95-64 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive. |
| Instance 0 Address: | 0x40010210 |
GPIO Input 3 (127-96)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RD3
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | RD3 | RO | GPIO127-96 Reads pin state - read only. Returns the pad pin state for pins 0-31 if the PINCFG's input enable (INPEN) is active and RDZERO is inactive. |
| Instance 0 Address: | 0x40010214 |
GPIO Output 0 (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WT0
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WT0 | RW | GPIO31-0 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status, including sets/clears through the WTS and WTC registers. |
| Instance 0 Address: | 0x40010218 |
GPIO Output 1 (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WT1
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WT1 | RW | GPIO63-32 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status, including sets/clears through the WTS and WTC registers. |
| Instance 0 Address: | 0x4001021C |
GPIO Output 2 (95-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WT2
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WT2 | RW | GPIO95-64 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status, including sets/clears through the WTS and WTC registers. |
| Instance 0 Address: | 0x40010220 |
GPIO Output 3 (127-96)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WT3
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WT3 | RW | GPIO127-96 Reads or writes pin state. Writes of 1 bits set output pad signal if the GPIO is enabled for output. Reads return status, including sets/clears through the WTS and WTC registers. |
| Instance 0 Address: | 0x40010224 |
GPIO Output Set 0 (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WTS0
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTS0 | RW | GPIO31-0 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT Register. |
| Instance 0 Address: | 0x40010228 |
GPIO Output Set 1 (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WTS1
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTS1 | RW | GPIO63-32 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT Register. |
| Instance 0 Address: | 0x4001022C |
GPIO Output Set 2 (95-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WTS2
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTS2 | RW | GPIO95-64 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT Register. |
| Instance 0 Address: | 0x40010230 |
GPIO Output Set 3 (127-96)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WTS3
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTS3 | RW | GPIO127-96 Sets pin state. Writing a 1 to any bit sets the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT Register. |
| Instance 0 Address: | 0x40010234 |
GPIO Output Clear 0 (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WTC0
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTC0 | RW | GPIO31-0 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT register. |
| Instance 0 Address: | 0x40010238 |
GPIO Output Clear 1 (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WTC1
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTC1 | RW | GPIO63-32 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT register. |
| Instance 0 Address: | 0x4001023C |
GPIO Output Clear 2 (95-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WTC2
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTC2 | RW | GPIO95-64 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT register. |
| Instance 0 Address: | 0x40010240 |
GPIO Output Clear 3 (127-96)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WTC3
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTC3 | RW | GPIO127-96 Clears pin state. Writing a 1 to any bit clears the corresponding bit in the WT register if the GPIO is enabled for output. Writing a value of 0 has no effect on the corresponding bit in the WT register. Status reads should be made via the WT register. |
| Instance 0 Address: | 0x40010244 |
GPIO Enable 0 (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| EN0
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | EN0 | RW | GPIO31-0 Enables tri-state pin output. Writing a 1 to any bit enables, and writing a 0 to any bit disables, the output for the corresponding GPIO. Reads return output enable/disable status of GPIO. |
| Instance 0 Address: | 0x40010248 |
GPIO Enable 1 (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| EN1
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | EN1 | RW | GPIO63-32 Enables tri-state pin output. Writing a 1 to any bit enables, and writing a 0 to any bit disables, the output for the corresponding GPIO. Reads return output enable/disable status of GPIO. |
| Instance 0 Address: | 0x4001024C |
GPIO Enable 2 (95-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| EN2
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | EN2 | RW | GPIO95-64 Enables tri-state pin output. Writing a 1 to any bit enables, and writing a 0 to any bit disables, the output for the corresponding GPIO. Reads return output enable/disable status of GPIO. |
| Instance 0 Address: | 0x40010250 |
GPIO Enable 3 (127-96)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| EN3
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | EN3 | RW | GPIO127-96 Enables tri-state pin output. Writing a 1 to any bit enables, and writing a 0 to any bit disables, the output for the corresponding GPIO. Reads return output enable/disable status of GPIO. |
| Instance 0 Address: | 0x40010254 |
GPIO Enable Set 0 (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENS0
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENS0 | RW | GPIO31-0 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register. |
| Instance 0 Address: | 0x40010258 |
GPIO Enable Set 1 (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENS1
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENS1 | RW | GPIO63-32 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register. |
| Instance 0 Address: | 0x4001025C |
GPIO Enable Set 2 (95-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENS2
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENS2 | RW | GPIO95-64 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register. |
| Instance 0 Address: | 0x40010260 |
GPIO Enable Set 3 (127-96)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENS3
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENS3 | RW | GPIO127-96 Sets pin tri-state output enables. Writing a 1 to any bit sets the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register. |
| Instance 0 Address: | 0x40010264 |
GPIO Enable Clear 0 (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENC0
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENC0 | RW | GPIO31-0 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register. |
| Instance 0 Address: | 0x40010268 |
GPIO Enable Clear 1 (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENC1
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENC1 | RW | GPIO63-32 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register. |
| Instance 0 Address: | 0x4001026C |
GPIO Enable Clear 2 (95-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENC2
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENC2 | RW | GPIO95-64 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register. |
| Instance 0 Address: | 0x40010270 |
GPIO Enable Clear 3 (127-96)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENC3
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENC3 | RW | GPIO127-96 Clears pin tri-state output enables. Writing a 1 to any bit clears the corresponding bit in the EN register. Writing a value of 0 has no effect on the corresponding bit in the EN register. Status reads should be made to the EN Register. |
| Instance 0 Address: | 0x40010274 |
IOM0 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM0IRQ
0x7f |
||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED. |
| 6:0 | IOM0IRQ | RW | IOM0 IRQ pad select. |
| Instance 0 Address: | 0x40010278 |
IOM1 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM1IRQ
0x3f |
||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM1IRQ | RW | IOM1 IRQ pad select. |
| Instance 0 Address: | 0x4001027C |
IOM2 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM2IRQ
0x3f |
||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM2IRQ | RW | IOM2 IRQ pad select. |
| Instance 0 Address: | 0x40010280 |
IOM3 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM3IRQ
0x3f |
||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM3IRQ | RW | IOM3 IRQ pad select. |
| Instance 0 Address: | 0x40010284 |
IOM4 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM4IRQ
0x3f |
||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM4IRQ | RW | IOM4 IRQ pad select. |
| Instance 0 Address: | 0x40010288 |
IOM5 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM5IRQ
0x3f |
||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM5IRQ | RW | IOM5 IRQ pad select. |
| Instance 0 Address: | 0x4001028C |
IOM6 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM6IRQ
0x3f |
||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM6IRQ | RW | IOM6 IRQ pad select. |
| Instance 0 Address: | 0x40010290 |
IOM7 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM7IRQ
0x3f |
||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM7IRQ | RW | IOM7 IRQ pad select. |
| Instance 0 Address: | 0x40010294 |
SDIF CD and WP Select.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
SDIFWP
0x7f |
RSVD
0x0 |
SDIFCD
0x7f |
||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:15 | RSVD | RO | RESERVED |
| 14:8 | SDIFWP | RW | SDIF WP pad select. |
| 7 | RSVD | RO | RESERVED |
| 6:0 | SDIFCD | RW | SDIF CD pad select. |
| Instance 0 Address: | 0x40010298 |
GPIO Observation mode sample
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
OBSDATA
0x0 |
||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | RSVD | RO | RESERVED |
| 15:0 | OBSDATA | RW | Sample of the data output on the GPIO observation port. May have async sampling issues, as the data is not synronized to the read operation. Intended for debug purposes only. |
| Instance 0 Address: | 0x4001029C |
Read only. Reflects the value of the input enable signals for pads 31-0 sent to the pad.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| IEDATA0
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | IEDATA0 | RO | 1 indicates the input_en is active and the value of the pad will be trasmitted to the internal logic within the device. |
| Instance 0 Address: | 0x400102A0 |
Read only. Reflects the value of the input enable signals for pads 63-32 sent to the pad.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| IEDATA1
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | IEDATA1 | RO | 1 indicates the input_en is active and the value of the pad will be trasmitted to the internal logic within the device. |
| Instance 0 Address: | 0x400102A4 |
Read only. Reflects the value of the input enable signals for pads 95-64 sent to the pad.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| IEDATA2
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | IEDATA2 | RO | 1 indicates the input_en is active and the value of the pad will be trasmitted to the internal logic within the device. |
| Instance 0 Address: | 0x400102A8 |
Read only. Reflects the value of the input enable signals for pads 127-96 sent to the pad.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| IEDATA3
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | IEDATA3 | RO | 1 indicates the input_en is active and the value of the pad will be trasmitted to the internal logic within the device. |
| Instance 0 Address: | 0x400102AC |
Read only. Reflects the value of the output enable signals for pads 31-0 sent to the pad.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| OEDATA0
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | OEDATA0 | RO | The signal is negative active, and a value of 0 indicates the output_en_ is active and the MCU will be driving the pad. |
| Instance 0 Address: | 0x400102B0 |
Read only. Reflects the value of the output enable signals for pads 63-32 sent to the pad.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| OEDATA1
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | OEDATA1 | RO | The signal is negative active, and a value of 0 indicates the output_en_ is active and the MCU will be driving the pad. |
| Instance 0 Address: | 0x400102B4 |
Read only. Reflects the value of the output enable signals for pads 95-64 sent to the pad.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| OEDATA2
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | OEDATA2 | RO | The signal is negative active, and a value of 0 indicates the output_en_ is active and the MCU will be driving the pad. |
| Instance 0 Address: | 0x400102B8 |
Read only. Reflects the value of the output enable signals for pads 127-96 sent to the pad.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| OEDATA3
0x0 |
|||||||||||||||||||||||||||||||
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | OEDATA3 | RO | The signal is negative active, and a value of 0 indicates the output_en_ is active and the MCU will be driving the pad. |
| Instance 0 Address: | 0x400102C0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO31
0x0 |
MCUN0GPIO30
0x0 |
MCUN0GPIO29
0x0 |
MCUN0GPIO28
0x0 |
MCUN0GPIO27
0x0 |
MCUN0GPIO26
0x0 |
MCUN0GPIO25
0x0 |
MCUN0GPIO24
0x0 |
MCUN0GPIO23
0x0 |
MCUN0GPIO22
0x0 |
MCUN0GPIO21
0x0 |
MCUN0GPIO20
0x0 |
MCUN0GPIO19
0x0 |
MCUN0GPIO18
0x0 |
MCUN0GPIO17
0x0 |
MCUN0GPIO16
0x0 |
MCUN0GPIO15
0x0 |
MCUN0GPIO14
0x0 |
MCUN0GPIO13
0x0 |
MCUN0GPIO12
0x0 |
MCUN0GPIO11
0x0 |
MCUN0GPIO10
0x0 |
MCUN0GPIO9
0x0 |
MCUN0GPIO8
0x0 |
MCUN0GPIO7
0x0 |
MCUN0GPIO6
0x0 |
MCUN0GPIO5
0x0 |
MCUN0GPIO4
0x0 |
MCUN0GPIO3
0x0 |
MCUN0GPIO2
0x0 |
MCUN0GPIO1
0x0 |
MCUN0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO31 | RW | GPIO31 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO30 | RW | GPIO30 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO29 | RW | GPIO29 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO28 | RW | GPIO28 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO27 | RW | GPIO27 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO26 | RW | GPIO26 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO25 | RW | GPIO25 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO24 | RW | GPIO24 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO23 | RW | GPIO23 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO22 | RW | GPIO22 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO21 | RW | GPIO21 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO20 | RW | GPIO20 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO19 | RW | GPIO19 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO18 | RW | GPIO18 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO17 | RW | GPIO17 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO16 | RW | GPIO16 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO15 | RW | GPIO15 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO14 | RW | GPIO14 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO13 | RW | GPIO13 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO12 | RW | GPIO12 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO11 | RW | GPIO11 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO10 | RW | GPIO10 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO9 | RW | GPIO9 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO8 | RW | GPIO8 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO7 | RW | GPIO7 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO6 | RW | GPIO6 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO5 | RW | GPIO5 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO4 | RW | GPIO4 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO3 | RW | GPIO3 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO2 | RW | GPIO2 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO1 | RW | GPIO1 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO0 | RW | GPIO0 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102C4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO31
0x0 |
MCUN0GPIO30
0x0 |
MCUN0GPIO29
0x0 |
MCUN0GPIO28
0x0 |
MCUN0GPIO27
0x0 |
MCUN0GPIO26
0x0 |
MCUN0GPIO25
0x0 |
MCUN0GPIO24
0x0 |
MCUN0GPIO23
0x0 |
MCUN0GPIO22
0x0 |
MCUN0GPIO21
0x0 |
MCUN0GPIO20
0x0 |
MCUN0GPIO19
0x0 |
MCUN0GPIO18
0x0 |
MCUN0GPIO17
0x0 |
MCUN0GPIO16
0x0 |
MCUN0GPIO15
0x0 |
MCUN0GPIO14
0x0 |
MCUN0GPIO13
0x0 |
MCUN0GPIO12
0x0 |
MCUN0GPIO11
0x0 |
MCUN0GPIO10
0x0 |
MCUN0GPIO9
0x0 |
MCUN0GPIO8
0x0 |
MCUN0GPIO7
0x0 |
MCUN0GPIO6
0x0 |
MCUN0GPIO5
0x0 |
MCUN0GPIO4
0x0 |
MCUN0GPIO3
0x0 |
MCUN0GPIO2
0x0 |
MCUN0GPIO1
0x0 |
MCUN0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO31 | RW | GPIO31 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO30 | RW | GPIO30 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO29 | RW | GPIO29 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO28 | RW | GPIO28 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO27 | RW | GPIO27 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO26 | RW | GPIO26 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO25 | RW | GPIO25 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO24 | RW | GPIO24 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO23 | RW | GPIO23 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO22 | RW | GPIO22 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO21 | RW | GPIO21 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO20 | RW | GPIO20 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO19 | RW | GPIO19 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO18 | RW | GPIO18 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO17 | RW | GPIO17 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO16 | RW | GPIO16 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO15 | RW | GPIO15 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO14 | RW | GPIO14 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO13 | RW | GPIO13 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO12 | RW | GPIO12 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO11 | RW | GPIO11 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO10 | RW | GPIO10 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO9 | RW | GPIO9 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO8 | RW | GPIO8 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO7 | RW | GPIO7 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO6 | RW | GPIO6 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO5 | RW | GPIO5 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO4 | RW | GPIO4 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO3 | RW | GPIO3 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO2 | RW | GPIO2 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO1 | RW | GPIO1 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO0 | RW | GPIO0 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102C8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO31
0x0 |
MCUN0GPIO30
0x0 |
MCUN0GPIO29
0x0 |
MCUN0GPIO28
0x0 |
MCUN0GPIO27
0x0 |
MCUN0GPIO26
0x0 |
MCUN0GPIO25
0x0 |
MCUN0GPIO24
0x0 |
MCUN0GPIO23
0x0 |
MCUN0GPIO22
0x0 |
MCUN0GPIO21
0x0 |
MCUN0GPIO20
0x0 |
MCUN0GPIO19
0x0 |
MCUN0GPIO18
0x0 |
MCUN0GPIO17
0x0 |
MCUN0GPIO16
0x0 |
MCUN0GPIO15
0x0 |
MCUN0GPIO14
0x0 |
MCUN0GPIO13
0x0 |
MCUN0GPIO12
0x0 |
MCUN0GPIO11
0x0 |
MCUN0GPIO10
0x0 |
MCUN0GPIO9
0x0 |
MCUN0GPIO8
0x0 |
MCUN0GPIO7
0x0 |
MCUN0GPIO6
0x0 |
MCUN0GPIO5
0x0 |
MCUN0GPIO4
0x0 |
MCUN0GPIO3
0x0 |
MCUN0GPIO2
0x0 |
MCUN0GPIO1
0x0 |
MCUN0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO31 | RW | GPIO31 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO30 | RW | GPIO30 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO29 | RW | GPIO29 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO28 | RW | GPIO28 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO27 | RW | GPIO27 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO26 | RW | GPIO26 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO25 | RW | GPIO25 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO24 | RW | GPIO24 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO23 | RW | GPIO23 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO22 | RW | GPIO22 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO21 | RW | GPIO21 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO20 | RW | GPIO20 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO19 | RW | GPIO19 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO18 | RW | GPIO18 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO17 | RW | GPIO17 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO16 | RW | GPIO16 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO15 | RW | GPIO15 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO14 | RW | GPIO14 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO13 | RW | GPIO13 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO12 | RW | GPIO12 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO11 | RW | GPIO11 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO10 | RW | GPIO10 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO9 | RW | GPIO9 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO8 | RW | GPIO8 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO7 | RW | GPIO7 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO6 | RW | GPIO6 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO5 | RW | GPIO5 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO4 | RW | GPIO4 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO3 | RW | GPIO3 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO2 | RW | GPIO2 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO1 | RW | GPIO1 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO0 | RW | GPIO0 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102CC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO31
0x0 |
MCUN0GPIO30
0x0 |
MCUN0GPIO29
0x0 |
MCUN0GPIO28
0x0 |
MCUN0GPIO27
0x0 |
MCUN0GPIO26
0x0 |
MCUN0GPIO25
0x0 |
MCUN0GPIO24
0x0 |
MCUN0GPIO23
0x0 |
MCUN0GPIO22
0x0 |
MCUN0GPIO21
0x0 |
MCUN0GPIO20
0x0 |
MCUN0GPIO19
0x0 |
MCUN0GPIO18
0x0 |
MCUN0GPIO17
0x0 |
MCUN0GPIO16
0x0 |
MCUN0GPIO15
0x0 |
MCUN0GPIO14
0x0 |
MCUN0GPIO13
0x0 |
MCUN0GPIO12
0x0 |
MCUN0GPIO11
0x0 |
MCUN0GPIO10
0x0 |
MCUN0GPIO9
0x0 |
MCUN0GPIO8
0x0 |
MCUN0GPIO7
0x0 |
MCUN0GPIO6
0x0 |
MCUN0GPIO5
0x0 |
MCUN0GPIO4
0x0 |
MCUN0GPIO3
0x0 |
MCUN0GPIO2
0x0 |
MCUN0GPIO1
0x0 |
MCUN0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO31 | RW | GPIO31 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO30 | RW | GPIO30 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO29 | RW | GPIO29 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO28 | RW | GPIO28 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO27 | RW | GPIO27 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO26 | RW | GPIO26 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO25 | RW | GPIO25 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO24 | RW | GPIO24 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO23 | RW | GPIO23 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO22 | RW | GPIO22 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO21 | RW | GPIO21 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO20 | RW | GPIO20 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO19 | RW | GPIO19 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO18 | RW | GPIO18 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO17 | RW | GPIO17 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO16 | RW | GPIO16 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO15 | RW | GPIO15 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO14 | RW | GPIO14 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO13 | RW | GPIO13 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO12 | RW | GPIO12 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO11 | RW | GPIO11 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO10 | RW | GPIO10 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO9 | RW | GPIO9 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO8 | RW | GPIO8 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO7 | RW | GPIO7 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO6 | RW | GPIO6 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO5 | RW | GPIO5 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO4 | RW | GPIO4 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO3 | RW | GPIO3 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO2 | RW | GPIO2 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO1 | RW | GPIO1 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO0 | RW | GPIO0 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102D0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO63
0x0 |
MCUN0GPIO62
0x0 |
MCUN0GPIO61
0x0 |
MCUN0GPIO60
0x0 |
MCUN0GPIO59
0x0 |
MCUN0GPIO58
0x0 |
MCUN0GPIO57
0x0 |
MCUN0GPIO56
0x0 |
MCUN0GPIO55
0x0 |
MCUN0GPIO54
0x0 |
MCUN0GPIO53
0x0 |
MCUN0GPIO52
0x0 |
MCUN0GPIO51
0x0 |
MCUN0GPIO50
0x0 |
MCUN0GPIO49
0x0 |
MCUN0GPIO48
0x0 |
MCUN0GPIO47
0x0 |
MCUN0GPIO46
0x0 |
MCUN0GPIO45
0x0 |
MCUN0GPIO44
0x0 |
MCUN0GPIO43
0x0 |
MCUN0GPIO42
0x0 |
MCUN0GPIO41
0x0 |
MCUN0GPIO40
0x0 |
MCUN0GPIO39
0x0 |
MCUN0GPIO38
0x0 |
MCUN0GPIO37
0x0 |
MCUN0GPIO36
0x0 |
MCUN0GPIO35
0x0 |
MCUN0GPIO34
0x0 |
MCUN0GPIO33
0x0 |
MCUN0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO63 | RW | GPIO63 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO62 | RW | GPIO62 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO61 | RW | GPIO61 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO60 | RW | GPIO60 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO59 | RW | GPIO59 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO58 | RW | GPIO58 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO57 | RW | GPIO57 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO56 | RW | GPIO56 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO55 | RW | GPIO55 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO54 | RW | GPIO54 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO53 | RW | GPIO53 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO52 | RW | GPIO52 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO51 | RW | GPIO51 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO50 | RW | GPIO50 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO49 | RW | GPIO49 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO48 | RW | GPIO48 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO47 | RW | GPIO47 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO46 | RW | GPIO46 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO45 | RW | GPIO45 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO44 | RW | GPIO44 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO43 | RW | GPIO43 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO42 | RW | GPIO42 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO41 | RW | GPIO41 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO40 | RW | GPIO40 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO39 | RW | GPIO39 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO38 | RW | GPIO38 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO37 | RW | GPIO37 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO36 | RW | GPIO36 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO35 | RW | GPIO35 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO34 | RW | GPIO34 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO33 | RW | GPIO33 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO32 | RW | GPIO32 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102D4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO63
0x0 |
MCUN0GPIO62
0x0 |
MCUN0GPIO61
0x0 |
MCUN0GPIO60
0x0 |
MCUN0GPIO59
0x0 |
MCUN0GPIO58
0x0 |
MCUN0GPIO57
0x0 |
MCUN0GPIO56
0x0 |
MCUN0GPIO55
0x0 |
MCUN0GPIO54
0x0 |
MCUN0GPIO53
0x0 |
MCUN0GPIO52
0x0 |
MCUN0GPIO51
0x0 |
MCUN0GPIO50
0x0 |
MCUN0GPIO49
0x0 |
MCUN0GPIO48
0x0 |
MCUN0GPIO47
0x0 |
MCUN0GPIO46
0x0 |
MCUN0GPIO45
0x0 |
MCUN0GPIO44
0x0 |
MCUN0GPIO43
0x0 |
MCUN0GPIO42
0x0 |
MCUN0GPIO41
0x0 |
MCUN0GPIO40
0x0 |
MCUN0GPIO39
0x0 |
MCUN0GPIO38
0x0 |
MCUN0GPIO37
0x0 |
MCUN0GPIO36
0x0 |
MCUN0GPIO35
0x0 |
MCUN0GPIO34
0x0 |
MCUN0GPIO33
0x0 |
MCUN0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO63 | RW | GPIO63 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO62 | RW | GPIO62 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO61 | RW | GPIO61 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO60 | RW | GPIO60 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO59 | RW | GPIO59 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO58 | RW | GPIO58 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO57 | RW | GPIO57 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO56 | RW | GPIO56 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO55 | RW | GPIO55 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO54 | RW | GPIO54 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO53 | RW | GPIO53 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO52 | RW | GPIO52 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO51 | RW | GPIO51 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO50 | RW | GPIO50 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO49 | RW | GPIO49 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO48 | RW | GPIO48 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO47 | RW | GPIO47 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO46 | RW | GPIO46 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO45 | RW | GPIO45 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO44 | RW | GPIO44 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO43 | RW | GPIO43 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO42 | RW | GPIO42 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO41 | RW | GPIO41 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO40 | RW | GPIO40 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO39 | RW | GPIO39 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO38 | RW | GPIO38 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO37 | RW | GPIO37 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO36 | RW | GPIO36 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO35 | RW | GPIO35 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO34 | RW | GPIO34 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO33 | RW | GPIO33 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO32 | RW | GPIO32 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102D8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO63
0x0 |
MCUN0GPIO62
0x0 |
MCUN0GPIO61
0x0 |
MCUN0GPIO60
0x0 |
MCUN0GPIO59
0x0 |
MCUN0GPIO58
0x0 |
MCUN0GPIO57
0x0 |
MCUN0GPIO56
0x0 |
MCUN0GPIO55
0x0 |
MCUN0GPIO54
0x0 |
MCUN0GPIO53
0x0 |
MCUN0GPIO52
0x0 |
MCUN0GPIO51
0x0 |
MCUN0GPIO50
0x0 |
MCUN0GPIO49
0x0 |
MCUN0GPIO48
0x0 |
MCUN0GPIO47
0x0 |
MCUN0GPIO46
0x0 |
MCUN0GPIO45
0x0 |
MCUN0GPIO44
0x0 |
MCUN0GPIO43
0x0 |
MCUN0GPIO42
0x0 |
MCUN0GPIO41
0x0 |
MCUN0GPIO40
0x0 |
MCUN0GPIO39
0x0 |
MCUN0GPIO38
0x0 |
MCUN0GPIO37
0x0 |
MCUN0GPIO36
0x0 |
MCUN0GPIO35
0x0 |
MCUN0GPIO34
0x0 |
MCUN0GPIO33
0x0 |
MCUN0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO63 | RW | GPIO63 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO62 | RW | GPIO62 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO61 | RW | GPIO61 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO60 | RW | GPIO60 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO59 | RW | GPIO59 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO58 | RW | GPIO58 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO57 | RW | GPIO57 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO56 | RW | GPIO56 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO55 | RW | GPIO55 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO54 | RW | GPIO54 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO53 | RW | GPIO53 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO52 | RW | GPIO52 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO51 | RW | GPIO51 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO50 | RW | GPIO50 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO49 | RW | GPIO49 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO48 | RW | GPIO48 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO47 | RW | GPIO47 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO46 | RW | GPIO46 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO45 | RW | GPIO45 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO44 | RW | GPIO44 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO43 | RW | GPIO43 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO42 | RW | GPIO42 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO41 | RW | GPIO41 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO40 | RW | GPIO40 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO39 | RW | GPIO39 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO38 | RW | GPIO38 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO37 | RW | GPIO37 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO36 | RW | GPIO36 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO35 | RW | GPIO35 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO34 | RW | GPIO34 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO33 | RW | GPIO33 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO32 | RW | GPIO32 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102DC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO63
0x0 |
MCUN0GPIO62
0x0 |
MCUN0GPIO61
0x0 |
MCUN0GPIO60
0x0 |
MCUN0GPIO59
0x0 |
MCUN0GPIO58
0x0 |
MCUN0GPIO57
0x0 |
MCUN0GPIO56
0x0 |
MCUN0GPIO55
0x0 |
MCUN0GPIO54
0x0 |
MCUN0GPIO53
0x0 |
MCUN0GPIO52
0x0 |
MCUN0GPIO51
0x0 |
MCUN0GPIO50
0x0 |
MCUN0GPIO49
0x0 |
MCUN0GPIO48
0x0 |
MCUN0GPIO47
0x0 |
MCUN0GPIO46
0x0 |
MCUN0GPIO45
0x0 |
MCUN0GPIO44
0x0 |
MCUN0GPIO43
0x0 |
MCUN0GPIO42
0x0 |
MCUN0GPIO41
0x0 |
MCUN0GPIO40
0x0 |
MCUN0GPIO39
0x0 |
MCUN0GPIO38
0x0 |
MCUN0GPIO37
0x0 |
MCUN0GPIO36
0x0 |
MCUN0GPIO35
0x0 |
MCUN0GPIO34
0x0 |
MCUN0GPIO33
0x0 |
MCUN0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO63 | RW | GPIO63 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO62 | RW | GPIO62 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO61 | RW | GPIO61 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO60 | RW | GPIO60 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO59 | RW | GPIO59 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO58 | RW | GPIO58 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO57 | RW | GPIO57 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO56 | RW | GPIO56 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO55 | RW | GPIO55 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO54 | RW | GPIO54 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO53 | RW | GPIO53 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO52 | RW | GPIO52 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO51 | RW | GPIO51 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO50 | RW | GPIO50 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO49 | RW | GPIO49 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO48 | RW | GPIO48 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO47 | RW | GPIO47 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO46 | RW | GPIO46 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO45 | RW | GPIO45 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO44 | RW | GPIO44 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO43 | RW | GPIO43 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO42 | RW | GPIO42 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO41 | RW | GPIO41 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO40 | RW | GPIO40 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO39 | RW | GPIO39 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO38 | RW | GPIO38 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO37 | RW | GPIO37 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO36 | RW | GPIO36 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO35 | RW | GPIO35 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO34 | RW | GPIO34 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO33 | RW | GPIO33 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO32 | RW | GPIO32 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102E0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO95
0x0 |
MCUN0GPIO94
0x0 |
MCUN0GPIO93
0x0 |
MCUN0GPIO92
0x0 |
MCUN0GPIO91
0x0 |
MCUN0GPIO90
0x0 |
MCUN0GPIO89
0x0 |
MCUN0GPIO88
0x0 |
MCUN0GPIO87
0x0 |
MCUN0GPIO86
0x0 |
MCUN0GPIO85
0x0 |
MCUN0GPIO84
0x0 |
MCUN0GPIO83
0x0 |
MCUN0GPIO82
0x0 |
MCUN0GPIO81
0x0 |
MCUN0GPIO80
0x0 |
MCUN0GPIO79
0x0 |
MCUN0GPIO78
0x0 |
MCUN0GPIO77
0x0 |
MCUN0GPIO76
0x0 |
MCUN0GPIO75
0x0 |
MCUN0GPIO74
0x0 |
MCUN0GPIO73
0x0 |
MCUN0GPIO72
0x0 |
MCUN0GPIO71
0x0 |
MCUN0GPIO70
0x0 |
MCUN0GPIO69
0x0 |
MCUN0GPIO68
0x0 |
MCUN0GPIO67
0x0 |
MCUN0GPIO66
0x0 |
MCUN0GPIO65
0x0 |
MCUN0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO95 | RW | GPIO95 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO94 | RW | GPIO94 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO93 | RW | GPIO93 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO92 | RW | GPIO92 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO91 | RW | GPIO91 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO90 | RW | GPIO90 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO89 | RW | GPIO89 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO88 | RW | GPIO88 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO87 | RW | GPIO87 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO86 | RW | GPIO86 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO85 | RW | GPIO85 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO84 | RW | GPIO84 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO83 | RW | GPIO83 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO82 | RW | GPIO82 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO81 | RW | GPIO81 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO80 | RW | GPIO80 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO79 | RW | GPIO79 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO78 | RW | GPIO78 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO77 | RW | GPIO77 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO76 | RW | GPIO76 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO75 | RW | GPIO75 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO74 | RW | GPIO74 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO73 | RW | GPIO73 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO72 | RW | GPIO72 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO71 | RW | GPIO71 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO70 | RW | GPIO70 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO69 | RW | GPIO69 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO68 | RW | GPIO68 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO67 | RW | GPIO67 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO66 | RW | GPIO66 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO65 | RW | GPIO65 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO64 | RW | GPIO64 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102E4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO95
0x0 |
MCUN0GPIO94
0x0 |
MCUN0GPIO93
0x0 |
MCUN0GPIO92
0x0 |
MCUN0GPIO91
0x0 |
MCUN0GPIO90
0x0 |
MCUN0GPIO89
0x0 |
MCUN0GPIO88
0x0 |
MCUN0GPIO87
0x0 |
MCUN0GPIO86
0x0 |
MCUN0GPIO85
0x0 |
MCUN0GPIO84
0x0 |
MCUN0GPIO83
0x0 |
MCUN0GPIO82
0x0 |
MCUN0GPIO81
0x0 |
MCUN0GPIO80
0x0 |
MCUN0GPIO79
0x0 |
MCUN0GPIO78
0x0 |
MCUN0GPIO77
0x0 |
MCUN0GPIO76
0x0 |
MCUN0GPIO75
0x0 |
MCUN0GPIO74
0x0 |
MCUN0GPIO73
0x0 |
MCUN0GPIO72
0x0 |
MCUN0GPIO71
0x0 |
MCUN0GPIO70
0x0 |
MCUN0GPIO69
0x0 |
MCUN0GPIO68
0x0 |
MCUN0GPIO67
0x0 |
MCUN0GPIO66
0x0 |
MCUN0GPIO65
0x0 |
MCUN0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO95 | RW | GPIO95 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO94 | RW | GPIO94 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO93 | RW | GPIO93 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO92 | RW | GPIO92 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO91 | RW | GPIO91 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO90 | RW | GPIO90 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO89 | RW | GPIO89 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO88 | RW | GPIO88 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO87 | RW | GPIO87 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO86 | RW | GPIO86 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO85 | RW | GPIO85 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO84 | RW | GPIO84 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO83 | RW | GPIO83 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO82 | RW | GPIO82 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO81 | RW | GPIO81 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO80 | RW | GPIO80 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO79 | RW | GPIO79 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO78 | RW | GPIO78 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO77 | RW | GPIO77 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO76 | RW | GPIO76 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO75 | RW | GPIO75 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO74 | RW | GPIO74 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO73 | RW | GPIO73 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO72 | RW | GPIO72 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO71 | RW | GPIO71 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO70 | RW | GPIO70 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO69 | RW | GPIO69 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO68 | RW | GPIO68 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO67 | RW | GPIO67 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO66 | RW | GPIO66 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO65 | RW | GPIO65 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO64 | RW | GPIO64 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102E8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO95
0x0 |
MCUN0GPIO94
0x0 |
MCUN0GPIO93
0x0 |
MCUN0GPIO92
0x0 |
MCUN0GPIO91
0x0 |
MCUN0GPIO90
0x0 |
MCUN0GPIO89
0x0 |
MCUN0GPIO88
0x0 |
MCUN0GPIO87
0x0 |
MCUN0GPIO86
0x0 |
MCUN0GPIO85
0x0 |
MCUN0GPIO84
0x0 |
MCUN0GPIO83
0x0 |
MCUN0GPIO82
0x0 |
MCUN0GPIO81
0x0 |
MCUN0GPIO80
0x0 |
MCUN0GPIO79
0x0 |
MCUN0GPIO78
0x0 |
MCUN0GPIO77
0x0 |
MCUN0GPIO76
0x0 |
MCUN0GPIO75
0x0 |
MCUN0GPIO74
0x0 |
MCUN0GPIO73
0x0 |
MCUN0GPIO72
0x0 |
MCUN0GPIO71
0x0 |
MCUN0GPIO70
0x0 |
MCUN0GPIO69
0x0 |
MCUN0GPIO68
0x0 |
MCUN0GPIO67
0x0 |
MCUN0GPIO66
0x0 |
MCUN0GPIO65
0x0 |
MCUN0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO95 | RW | GPIO95 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO94 | RW | GPIO94 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO93 | RW | GPIO93 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO92 | RW | GPIO92 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO91 | RW | GPIO91 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO90 | RW | GPIO90 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO89 | RW | GPIO89 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO88 | RW | GPIO88 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO87 | RW | GPIO87 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO86 | RW | GPIO86 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO85 | RW | GPIO85 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO84 | RW | GPIO84 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO83 | RW | GPIO83 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO82 | RW | GPIO82 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO81 | RW | GPIO81 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO80 | RW | GPIO80 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO79 | RW | GPIO79 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO78 | RW | GPIO78 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO77 | RW | GPIO77 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO76 | RW | GPIO76 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO75 | RW | GPIO75 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO74 | RW | GPIO74 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO73 | RW | GPIO73 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO72 | RW | GPIO72 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO71 | RW | GPIO71 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO70 | RW | GPIO70 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO69 | RW | GPIO69 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO68 | RW | GPIO68 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO67 | RW | GPIO67 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO66 | RW | GPIO66 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO65 | RW | GPIO65 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO64 | RW | GPIO64 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102EC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO95
0x0 |
MCUN0GPIO94
0x0 |
MCUN0GPIO93
0x0 |
MCUN0GPIO92
0x0 |
MCUN0GPIO91
0x0 |
MCUN0GPIO90
0x0 |
MCUN0GPIO89
0x0 |
MCUN0GPIO88
0x0 |
MCUN0GPIO87
0x0 |
MCUN0GPIO86
0x0 |
MCUN0GPIO85
0x0 |
MCUN0GPIO84
0x0 |
MCUN0GPIO83
0x0 |
MCUN0GPIO82
0x0 |
MCUN0GPIO81
0x0 |
MCUN0GPIO80
0x0 |
MCUN0GPIO79
0x0 |
MCUN0GPIO78
0x0 |
MCUN0GPIO77
0x0 |
MCUN0GPIO76
0x0 |
MCUN0GPIO75
0x0 |
MCUN0GPIO74
0x0 |
MCUN0GPIO73
0x0 |
MCUN0GPIO72
0x0 |
MCUN0GPIO71
0x0 |
MCUN0GPIO70
0x0 |
MCUN0GPIO69
0x0 |
MCUN0GPIO68
0x0 |
MCUN0GPIO67
0x0 |
MCUN0GPIO66
0x0 |
MCUN0GPIO65
0x0 |
MCUN0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO95 | RW | GPIO95 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO94 | RW | GPIO94 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO93 | RW | GPIO93 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO92 | RW | GPIO92 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO91 | RW | GPIO91 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO90 | RW | GPIO90 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO89 | RW | GPIO89 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO88 | RW | GPIO88 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO87 | RW | GPIO87 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO86 | RW | GPIO86 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO85 | RW | GPIO85 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO84 | RW | GPIO84 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO83 | RW | GPIO83 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO82 | RW | GPIO82 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO81 | RW | GPIO81 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO80 | RW | GPIO80 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO79 | RW | GPIO79 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO78 | RW | GPIO78 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO77 | RW | GPIO77 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO76 | RW | GPIO76 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO75 | RW | GPIO75 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO74 | RW | GPIO74 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO73 | RW | GPIO73 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO72 | RW | GPIO72 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO71 | RW | GPIO71 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO70 | RW | GPIO70 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO69 | RW | GPIO69 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO68 | RW | GPIO68 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO67 | RW | GPIO67 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO66 | RW | GPIO66 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO65 | RW | GPIO65 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO64 | RW | GPIO64 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102F0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO127
0x0 |
MCUN0GPIO126
0x0 |
MCUN0GPIO125
0x0 |
MCUN0GPIO124
0x0 |
MCUN0GPIO123
0x0 |
MCUN0GPIO122
0x0 |
MCUN0GPIO121
0x0 |
MCUN0GPIO120
0x0 |
MCUN0GPIO119
0x0 |
MCUN0GPIO118
0x0 |
MCUN0GPIO117
0x0 |
MCUN0GPIO116
0x0 |
MCUN0GPIO115
0x0 |
MCUN0GPIO114
0x0 |
MCUN0GPIO113
0x0 |
MCUN0GPIO112
0x0 |
MCUN0GPIO111
0x0 |
MCUN0GPIO110
0x0 |
MCUN0GPIO109
0x0 |
MCUN0GPIO108
0x0 |
MCUN0GPIO107
0x0 |
MCUN0GPIO106
0x0 |
MCUN0GPIO105
0x0 |
MCUN0GPIO104
0x0 |
MCUN0GPIO103
0x0 |
MCUN0GPIO102
0x0 |
MCUN0GPIO101
0x0 |
MCUN0GPIO100
0x0 |
MCUN0GPIO99
0x0 |
MCUN0GPIO98
0x0 |
MCUN0GPIO97
0x0 |
MCUN0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO127 | RW | GPIO127 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO126 | RW | GPIO126 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO125 | RW | GPIO125 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO124 | RW | GPIO124 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO123 | RW | GPIO123 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO122 | RW | GPIO122 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO121 | RW | GPIO121 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO120 | RW | GPIO120 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO119 | RW | GPIO119 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO118 | RW | GPIO118 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO117 | RW | GPIO117 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO116 | RW | GPIO116 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO115 | RW | GPIO115 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO114 | RW | GPIO114 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO113 | RW | GPIO113 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO112 | RW | GPIO112 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO111 | RW | GPIO111 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO110 | RW | GPIO110 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO109 | RW | GPIO109 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO108 | RW | GPIO108 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO107 | RW | GPIO107 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO106 | RW | GPIO106 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO105 | RW | GPIO105 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO104 | RW | GPIO104 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO103 | RW | GPIO103 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO102 | RW | GPIO102 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO101 | RW | GPIO101 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO100 | RW | GPIO100 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO99 | RW | GPIO99 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO98 | RW | GPIO98 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO97 | RW | GPIO97 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO96 | RW | GPIO96 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102F4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO127
0x0 |
MCUN0GPIO126
0x0 |
MCUN0GPIO125
0x0 |
MCUN0GPIO124
0x0 |
MCUN0GPIO123
0x0 |
MCUN0GPIO122
0x0 |
MCUN0GPIO121
0x0 |
MCUN0GPIO120
0x0 |
MCUN0GPIO119
0x0 |
MCUN0GPIO118
0x0 |
MCUN0GPIO117
0x0 |
MCUN0GPIO116
0x0 |
MCUN0GPIO115
0x0 |
MCUN0GPIO114
0x0 |
MCUN0GPIO113
0x0 |
MCUN0GPIO112
0x0 |
MCUN0GPIO111
0x0 |
MCUN0GPIO110
0x0 |
MCUN0GPIO109
0x0 |
MCUN0GPIO108
0x0 |
MCUN0GPIO107
0x0 |
MCUN0GPIO106
0x0 |
MCUN0GPIO105
0x0 |
MCUN0GPIO104
0x0 |
MCUN0GPIO103
0x0 |
MCUN0GPIO102
0x0 |
MCUN0GPIO101
0x0 |
MCUN0GPIO100
0x0 |
MCUN0GPIO99
0x0 |
MCUN0GPIO98
0x0 |
MCUN0GPIO97
0x0 |
MCUN0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO127 | RW | GPIO127 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO126 | RW | GPIO126 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO125 | RW | GPIO125 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO124 | RW | GPIO124 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO123 | RW | GPIO123 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO122 | RW | GPIO122 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO121 | RW | GPIO121 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO120 | RW | GPIO120 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO119 | RW | GPIO119 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO118 | RW | GPIO118 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO117 | RW | GPIO117 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO116 | RW | GPIO116 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO115 | RW | GPIO115 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO114 | RW | GPIO114 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO113 | RW | GPIO113 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO112 | RW | GPIO112 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO111 | RW | GPIO111 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO110 | RW | GPIO110 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO109 | RW | GPIO109 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO108 | RW | GPIO108 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO107 | RW | GPIO107 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO106 | RW | GPIO106 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO105 | RW | GPIO105 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO104 | RW | GPIO104 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO103 | RW | GPIO103 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO102 | RW | GPIO102 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO101 | RW | GPIO101 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO100 | RW | GPIO100 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO99 | RW | GPIO99 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO98 | RW | GPIO98 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO97 | RW | GPIO97 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO96 | RW | GPIO96 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102F8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO127
0x0 |
MCUN0GPIO126
0x0 |
MCUN0GPIO125
0x0 |
MCUN0GPIO124
0x0 |
MCUN0GPIO123
0x0 |
MCUN0GPIO122
0x0 |
MCUN0GPIO121
0x0 |
MCUN0GPIO120
0x0 |
MCUN0GPIO119
0x0 |
MCUN0GPIO118
0x0 |
MCUN0GPIO117
0x0 |
MCUN0GPIO116
0x0 |
MCUN0GPIO115
0x0 |
MCUN0GPIO114
0x0 |
MCUN0GPIO113
0x0 |
MCUN0GPIO112
0x0 |
MCUN0GPIO111
0x0 |
MCUN0GPIO110
0x0 |
MCUN0GPIO109
0x0 |
MCUN0GPIO108
0x0 |
MCUN0GPIO107
0x0 |
MCUN0GPIO106
0x0 |
MCUN0GPIO105
0x0 |
MCUN0GPIO104
0x0 |
MCUN0GPIO103
0x0 |
MCUN0GPIO102
0x0 |
MCUN0GPIO101
0x0 |
MCUN0GPIO100
0x0 |
MCUN0GPIO99
0x0 |
MCUN0GPIO98
0x0 |
MCUN0GPIO97
0x0 |
MCUN0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO127 | RW | GPIO127 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO126 | RW | GPIO126 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO125 | RW | GPIO125 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO124 | RW | GPIO124 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO123 | RW | GPIO123 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO122 | RW | GPIO122 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO121 | RW | GPIO121 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO120 | RW | GPIO120 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO119 | RW | GPIO119 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO118 | RW | GPIO118 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO117 | RW | GPIO117 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO116 | RW | GPIO116 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO115 | RW | GPIO115 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO114 | RW | GPIO114 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO113 | RW | GPIO113 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO112 | RW | GPIO112 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO111 | RW | GPIO111 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO110 | RW | GPIO110 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO109 | RW | GPIO109 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO108 | RW | GPIO108 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO107 | RW | GPIO107 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO106 | RW | GPIO106 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO105 | RW | GPIO105 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO104 | RW | GPIO104 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO103 | RW | GPIO103 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO102 | RW | GPIO102 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO101 | RW | GPIO101 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO100 | RW | GPIO100 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO99 | RW | GPIO99 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO98 | RW | GPIO98 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO97 | RW | GPIO97 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO96 | RW | GPIO96 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x400102FC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN0GPIO127
0x0 |
MCUN0GPIO126
0x0 |
MCUN0GPIO125
0x0 |
MCUN0GPIO124
0x0 |
MCUN0GPIO123
0x0 |
MCUN0GPIO122
0x0 |
MCUN0GPIO121
0x0 |
MCUN0GPIO120
0x0 |
MCUN0GPIO119
0x0 |
MCUN0GPIO118
0x0 |
MCUN0GPIO117
0x0 |
MCUN0GPIO116
0x0 |
MCUN0GPIO115
0x0 |
MCUN0GPIO114
0x0 |
MCUN0GPIO113
0x0 |
MCUN0GPIO112
0x0 |
MCUN0GPIO111
0x0 |
MCUN0GPIO110
0x0 |
MCUN0GPIO109
0x0 |
MCUN0GPIO108
0x0 |
MCUN0GPIO107
0x0 |
MCUN0GPIO106
0x0 |
MCUN0GPIO105
0x0 |
MCUN0GPIO104
0x0 |
MCUN0GPIO103
0x0 |
MCUN0GPIO102
0x0 |
MCUN0GPIO101
0x0 |
MCUN0GPIO100
0x0 |
MCUN0GPIO99
0x0 |
MCUN0GPIO98
0x0 |
MCUN0GPIO97
0x0 |
MCUN0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN0GPIO127 | RW | GPIO127 MCU N0-priority interrupt. |
| 30 | MCUN0GPIO126 | RW | GPIO126 MCU N0-priority interrupt. |
| 29 | MCUN0GPIO125 | RW | GPIO125 MCU N0-priority interrupt. |
| 28 | MCUN0GPIO124 | RW | GPIO124 MCU N0-priority interrupt. |
| 27 | MCUN0GPIO123 | RW | GPIO123 MCU N0-priority interrupt. |
| 26 | MCUN0GPIO122 | RW | GPIO122 MCU N0-priority interrupt. |
| 25 | MCUN0GPIO121 | RW | GPIO121 MCU N0-priority interrupt. |
| 24 | MCUN0GPIO120 | RW | GPIO120 MCU N0-priority interrupt. |
| 23 | MCUN0GPIO119 | RW | GPIO119 MCU N0-priority interrupt. |
| 22 | MCUN0GPIO118 | RW | GPIO118 MCU N0-priority interrupt. |
| 21 | MCUN0GPIO117 | RW | GPIO117 MCU N0-priority interrupt. |
| 20 | MCUN0GPIO116 | RW | GPIO116 MCU N0-priority interrupt. |
| 19 | MCUN0GPIO115 | RW | GPIO115 MCU N0-priority interrupt. |
| 18 | MCUN0GPIO114 | RW | GPIO114 MCU N0-priority interrupt. |
| 17 | MCUN0GPIO113 | RW | GPIO113 MCU N0-priority interrupt. |
| 16 | MCUN0GPIO112 | RW | GPIO112 MCU N0-priority interrupt. |
| 15 | MCUN0GPIO111 | RW | GPIO111 MCU N0-priority interrupt. |
| 14 | MCUN0GPIO110 | RW | GPIO110 MCU N0-priority interrupt. |
| 13 | MCUN0GPIO109 | RW | GPIO109 MCU N0-priority interrupt. |
| 12 | MCUN0GPIO108 | RW | GPIO108 MCU N0-priority interrupt. |
| 11 | MCUN0GPIO107 | RW | GPIO107 MCU N0-priority interrupt. |
| 10 | MCUN0GPIO106 | RW | GPIO106 MCU N0-priority interrupt. |
| 9 | MCUN0GPIO105 | RW | GPIO105 MCU N0-priority interrupt. |
| 8 | MCUN0GPIO104 | RW | GPIO104 MCU N0-priority interrupt. |
| 7 | MCUN0GPIO103 | RW | GPIO103 MCU N0-priority interrupt. |
| 6 | MCUN0GPIO102 | RW | GPIO102 MCU N0-priority interrupt. |
| 5 | MCUN0GPIO101 | RW | GPIO101 MCU N0-priority interrupt. |
| 4 | MCUN0GPIO100 | RW | GPIO100 MCU N0-priority interrupt. |
| 3 | MCUN0GPIO99 | RW | GPIO99 MCU N0-priority interrupt. |
| 2 | MCUN0GPIO98 | RW | GPIO98 MCU N0-priority interrupt. |
| 1 | MCUN0GPIO97 | RW | GPIO97 MCU N0-priority interrupt. |
| 0 | MCUN0GPIO96 | RW | GPIO96 MCU N0-priority interrupt. |
| Instance 0 Address: | 0x40010300 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO31
0x0 |
MCUN1GPIO30
0x0 |
MCUN1GPIO29
0x0 |
MCUN1GPIO28
0x0 |
MCUN1GPIO27
0x0 |
MCUN1GPIO26
0x0 |
MCUN1GPIO25
0x0 |
MCUN1GPIO24
0x0 |
MCUN1GPIO23
0x0 |
MCUN1GPIO22
0x0 |
MCUN1GPIO21
0x0 |
MCUN1GPIO20
0x0 |
MCUN1GPIO19
0x0 |
MCUN1GPIO18
0x0 |
MCUN1GPIO17
0x0 |
MCUN1GPIO16
0x0 |
MCUN1GPIO15
0x0 |
MCUN1GPIO14
0x0 |
MCUN1GPIO13
0x0 |
MCUN1GPIO12
0x0 |
MCUN1GPIO11
0x0 |
MCUN1GPIO10
0x0 |
MCUN1GPIO9
0x0 |
MCUN1GPIO8
0x0 |
MCUN1GPIO7
0x0 |
MCUN1GPIO6
0x0 |
MCUN1GPIO5
0x0 |
MCUN1GPIO4
0x0 |
MCUN1GPIO3
0x0 |
MCUN1GPIO2
0x0 |
MCUN1GPIO1
0x0 |
MCUN1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO31 | RW | GPIO31 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO30 | RW | GPIO30 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO29 | RW | GPIO29 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO28 | RW | GPIO28 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO27 | RW | GPIO27 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO26 | RW | GPIO26 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO25 | RW | GPIO25 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO24 | RW | GPIO24 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO23 | RW | GPIO23 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO22 | RW | GPIO22 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO21 | RW | GPIO21 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO20 | RW | GPIO20 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO19 | RW | GPIO19 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO18 | RW | GPIO18 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO17 | RW | GPIO17 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO16 | RW | GPIO16 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO15 | RW | GPIO15 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO14 | RW | GPIO14 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO13 | RW | GPIO13 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO12 | RW | GPIO12 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO11 | RW | GPIO11 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO10 | RW | GPIO10 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO9 | RW | GPIO9 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO8 | RW | GPIO8 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO7 | RW | GPIO7 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO6 | RW | GPIO6 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO5 | RW | GPIO5 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO4 | RW | GPIO4 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO3 | RW | GPIO3 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO2 | RW | GPIO2 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO1 | RW | GPIO1 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO0 | RW | GPIO0 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010304 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO31
0x0 |
MCUN1GPIO30
0x0 |
MCUN1GPIO29
0x0 |
MCUN1GPIO28
0x0 |
MCUN1GPIO27
0x0 |
MCUN1GPIO26
0x0 |
MCUN1GPIO25
0x0 |
MCUN1GPIO24
0x0 |
MCUN1GPIO23
0x0 |
MCUN1GPIO22
0x0 |
MCUN1GPIO21
0x0 |
MCUN1GPIO20
0x0 |
MCUN1GPIO19
0x0 |
MCUN1GPIO18
0x0 |
MCUN1GPIO17
0x0 |
MCUN1GPIO16
0x0 |
MCUN1GPIO15
0x0 |
MCUN1GPIO14
0x0 |
MCUN1GPIO13
0x0 |
MCUN1GPIO12
0x0 |
MCUN1GPIO11
0x0 |
MCUN1GPIO10
0x0 |
MCUN1GPIO9
0x0 |
MCUN1GPIO8
0x0 |
MCUN1GPIO7
0x0 |
MCUN1GPIO6
0x0 |
MCUN1GPIO5
0x0 |
MCUN1GPIO4
0x0 |
MCUN1GPIO3
0x0 |
MCUN1GPIO2
0x0 |
MCUN1GPIO1
0x0 |
MCUN1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO31 | RW | GPIO31 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO30 | RW | GPIO30 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO29 | RW | GPIO29 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO28 | RW | GPIO28 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO27 | RW | GPIO27 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO26 | RW | GPIO26 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO25 | RW | GPIO25 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO24 | RW | GPIO24 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO23 | RW | GPIO23 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO22 | RW | GPIO22 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO21 | RW | GPIO21 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO20 | RW | GPIO20 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO19 | RW | GPIO19 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO18 | RW | GPIO18 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO17 | RW | GPIO17 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO16 | RW | GPIO16 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO15 | RW | GPIO15 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO14 | RW | GPIO14 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO13 | RW | GPIO13 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO12 | RW | GPIO12 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO11 | RW | GPIO11 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO10 | RW | GPIO10 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO9 | RW | GPIO9 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO8 | RW | GPIO8 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO7 | RW | GPIO7 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO6 | RW | GPIO6 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO5 | RW | GPIO5 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO4 | RW | GPIO4 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO3 | RW | GPIO3 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO2 | RW | GPIO2 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO1 | RW | GPIO1 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO0 | RW | GPIO0 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010308 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO31
0x0 |
MCUN1GPIO30
0x0 |
MCUN1GPIO29
0x0 |
MCUN1GPIO28
0x0 |
MCUN1GPIO27
0x0 |
MCUN1GPIO26
0x0 |
MCUN1GPIO25
0x0 |
MCUN1GPIO24
0x0 |
MCUN1GPIO23
0x0 |
MCUN1GPIO22
0x0 |
MCUN1GPIO21
0x0 |
MCUN1GPIO20
0x0 |
MCUN1GPIO19
0x0 |
MCUN1GPIO18
0x0 |
MCUN1GPIO17
0x0 |
MCUN1GPIO16
0x0 |
MCUN1GPIO15
0x0 |
MCUN1GPIO14
0x0 |
MCUN1GPIO13
0x0 |
MCUN1GPIO12
0x0 |
MCUN1GPIO11
0x0 |
MCUN1GPIO10
0x0 |
MCUN1GPIO9
0x0 |
MCUN1GPIO8
0x0 |
MCUN1GPIO7
0x0 |
MCUN1GPIO6
0x0 |
MCUN1GPIO5
0x0 |
MCUN1GPIO4
0x0 |
MCUN1GPIO3
0x0 |
MCUN1GPIO2
0x0 |
MCUN1GPIO1
0x0 |
MCUN1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO31 | RW | GPIO31 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO30 | RW | GPIO30 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO29 | RW | GPIO29 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO28 | RW | GPIO28 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO27 | RW | GPIO27 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO26 | RW | GPIO26 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO25 | RW | GPIO25 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO24 | RW | GPIO24 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO23 | RW | GPIO23 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO22 | RW | GPIO22 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO21 | RW | GPIO21 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO20 | RW | GPIO20 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO19 | RW | GPIO19 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO18 | RW | GPIO18 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO17 | RW | GPIO17 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO16 | RW | GPIO16 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO15 | RW | GPIO15 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO14 | RW | GPIO14 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO13 | RW | GPIO13 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO12 | RW | GPIO12 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO11 | RW | GPIO11 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO10 | RW | GPIO10 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO9 | RW | GPIO9 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO8 | RW | GPIO8 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO7 | RW | GPIO7 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO6 | RW | GPIO6 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO5 | RW | GPIO5 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO4 | RW | GPIO4 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO3 | RW | GPIO3 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO2 | RW | GPIO2 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO1 | RW | GPIO1 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO0 | RW | GPIO0 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x4001030C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO31
0x0 |
MCUN1GPIO30
0x0 |
MCUN1GPIO29
0x0 |
MCUN1GPIO28
0x0 |
MCUN1GPIO27
0x0 |
MCUN1GPIO26
0x0 |
MCUN1GPIO25
0x0 |
MCUN1GPIO24
0x0 |
MCUN1GPIO23
0x0 |
MCUN1GPIO22
0x0 |
MCUN1GPIO21
0x0 |
MCUN1GPIO20
0x0 |
MCUN1GPIO19
0x0 |
MCUN1GPIO18
0x0 |
MCUN1GPIO17
0x0 |
MCUN1GPIO16
0x0 |
MCUN1GPIO15
0x0 |
MCUN1GPIO14
0x0 |
MCUN1GPIO13
0x0 |
MCUN1GPIO12
0x0 |
MCUN1GPIO11
0x0 |
MCUN1GPIO10
0x0 |
MCUN1GPIO9
0x0 |
MCUN1GPIO8
0x0 |
MCUN1GPIO7
0x0 |
MCUN1GPIO6
0x0 |
MCUN1GPIO5
0x0 |
MCUN1GPIO4
0x0 |
MCUN1GPIO3
0x0 |
MCUN1GPIO2
0x0 |
MCUN1GPIO1
0x0 |
MCUN1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO31 | RW | GPIO31 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO30 | RW | GPIO30 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO29 | RW | GPIO29 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO28 | RW | GPIO28 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO27 | RW | GPIO27 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO26 | RW | GPIO26 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO25 | RW | GPIO25 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO24 | RW | GPIO24 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO23 | RW | GPIO23 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO22 | RW | GPIO22 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO21 | RW | GPIO21 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO20 | RW | GPIO20 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO19 | RW | GPIO19 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO18 | RW | GPIO18 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO17 | RW | GPIO17 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO16 | RW | GPIO16 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO15 | RW | GPIO15 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO14 | RW | GPIO14 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO13 | RW | GPIO13 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO12 | RW | GPIO12 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO11 | RW | GPIO11 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO10 | RW | GPIO10 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO9 | RW | GPIO9 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO8 | RW | GPIO8 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO7 | RW | GPIO7 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO6 | RW | GPIO6 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO5 | RW | GPIO5 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO4 | RW | GPIO4 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO3 | RW | GPIO3 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO2 | RW | GPIO2 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO1 | RW | GPIO1 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO0 | RW | GPIO0 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010310 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO63
0x0 |
MCUN1GPIO62
0x0 |
MCUN1GPIO61
0x0 |
MCUN1GPIO60
0x0 |
MCUN1GPIO59
0x0 |
MCUN1GPIO58
0x0 |
MCUN1GPIO57
0x0 |
MCUN1GPIO56
0x0 |
MCUN1GPIO55
0x0 |
MCUN1GPIO54
0x0 |
MCUN1GPIO53
0x0 |
MCUN1GPIO52
0x0 |
MCUN1GPIO51
0x0 |
MCUN1GPIO50
0x0 |
MCUN1GPIO49
0x0 |
MCUN1GPIO48
0x0 |
MCUN1GPIO47
0x0 |
MCUN1GPIO46
0x0 |
MCUN1GPIO45
0x0 |
MCUN1GPIO44
0x0 |
MCUN1GPIO43
0x0 |
MCUN1GPIO42
0x0 |
MCUN1GPIO41
0x0 |
MCUN1GPIO40
0x0 |
MCUN1GPIO39
0x0 |
MCUN1GPIO38
0x0 |
MCUN1GPIO37
0x0 |
MCUN1GPIO36
0x0 |
MCUN1GPIO35
0x0 |
MCUN1GPIO34
0x0 |
MCUN1GPIO33
0x0 |
MCUN1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO63 | RW | GPIO63 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO62 | RW | GPIO62 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO61 | RW | GPIO61 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO60 | RW | GPIO60 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO59 | RW | GPIO59 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO58 | RW | GPIO58 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO57 | RW | GPIO57 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO56 | RW | GPIO56 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO55 | RW | GPIO55 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO54 | RW | GPIO54 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO53 | RW | GPIO53 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO52 | RW | GPIO52 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO51 | RW | GPIO51 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO50 | RW | GPIO50 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO49 | RW | GPIO49 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO48 | RW | GPIO48 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO47 | RW | GPIO47 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO46 | RW | GPIO46 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO45 | RW | GPIO45 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO44 | RW | GPIO44 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO43 | RW | GPIO43 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO42 | RW | GPIO42 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO41 | RW | GPIO41 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO40 | RW | GPIO40 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO39 | RW | GPIO39 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO38 | RW | GPIO38 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO37 | RW | GPIO37 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO36 | RW | GPIO36 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO35 | RW | GPIO35 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO34 | RW | GPIO34 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO33 | RW | GPIO33 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO32 | RW | GPIO32 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010314 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO63
0x0 |
MCUN1GPIO62
0x0 |
MCUN1GPIO61
0x0 |
MCUN1GPIO60
0x0 |
MCUN1GPIO59
0x0 |
MCUN1GPIO58
0x0 |
MCUN1GPIO57
0x0 |
MCUN1GPIO56
0x0 |
MCUN1GPIO55
0x0 |
MCUN1GPIO54
0x0 |
MCUN1GPIO53
0x0 |
MCUN1GPIO52
0x0 |
MCUN1GPIO51
0x0 |
MCUN1GPIO50
0x0 |
MCUN1GPIO49
0x0 |
MCUN1GPIO48
0x0 |
MCUN1GPIO47
0x0 |
MCUN1GPIO46
0x0 |
MCUN1GPIO45
0x0 |
MCUN1GPIO44
0x0 |
MCUN1GPIO43
0x0 |
MCUN1GPIO42
0x0 |
MCUN1GPIO41
0x0 |
MCUN1GPIO40
0x0 |
MCUN1GPIO39
0x0 |
MCUN1GPIO38
0x0 |
MCUN1GPIO37
0x0 |
MCUN1GPIO36
0x0 |
MCUN1GPIO35
0x0 |
MCUN1GPIO34
0x0 |
MCUN1GPIO33
0x0 |
MCUN1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO63 | RW | GPIO63 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO62 | RW | GPIO62 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO61 | RW | GPIO61 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO60 | RW | GPIO60 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO59 | RW | GPIO59 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO58 | RW | GPIO58 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO57 | RW | GPIO57 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO56 | RW | GPIO56 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO55 | RW | GPIO55 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO54 | RW | GPIO54 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO53 | RW | GPIO53 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO52 | RW | GPIO52 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO51 | RW | GPIO51 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO50 | RW | GPIO50 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO49 | RW | GPIO49 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO48 | RW | GPIO48 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO47 | RW | GPIO47 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO46 | RW | GPIO46 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO45 | RW | GPIO45 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO44 | RW | GPIO44 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO43 | RW | GPIO43 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO42 | RW | GPIO42 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO41 | RW | GPIO41 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO40 | RW | GPIO40 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO39 | RW | GPIO39 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO38 | RW | GPIO38 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO37 | RW | GPIO37 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO36 | RW | GPIO36 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO35 | RW | GPIO35 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO34 | RW | GPIO34 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO33 | RW | GPIO33 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO32 | RW | GPIO32 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010318 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO63
0x0 |
MCUN1GPIO62
0x0 |
MCUN1GPIO61
0x0 |
MCUN1GPIO60
0x0 |
MCUN1GPIO59
0x0 |
MCUN1GPIO58
0x0 |
MCUN1GPIO57
0x0 |
MCUN1GPIO56
0x0 |
MCUN1GPIO55
0x0 |
MCUN1GPIO54
0x0 |
MCUN1GPIO53
0x0 |
MCUN1GPIO52
0x0 |
MCUN1GPIO51
0x0 |
MCUN1GPIO50
0x0 |
MCUN1GPIO49
0x0 |
MCUN1GPIO48
0x0 |
MCUN1GPIO47
0x0 |
MCUN1GPIO46
0x0 |
MCUN1GPIO45
0x0 |
MCUN1GPIO44
0x0 |
MCUN1GPIO43
0x0 |
MCUN1GPIO42
0x0 |
MCUN1GPIO41
0x0 |
MCUN1GPIO40
0x0 |
MCUN1GPIO39
0x0 |
MCUN1GPIO38
0x0 |
MCUN1GPIO37
0x0 |
MCUN1GPIO36
0x0 |
MCUN1GPIO35
0x0 |
MCUN1GPIO34
0x0 |
MCUN1GPIO33
0x0 |
MCUN1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO63 | RW | GPIO63 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO62 | RW | GPIO62 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO61 | RW | GPIO61 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO60 | RW | GPIO60 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO59 | RW | GPIO59 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO58 | RW | GPIO58 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO57 | RW | GPIO57 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO56 | RW | GPIO56 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO55 | RW | GPIO55 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO54 | RW | GPIO54 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO53 | RW | GPIO53 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO52 | RW | GPIO52 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO51 | RW | GPIO51 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO50 | RW | GPIO50 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO49 | RW | GPIO49 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO48 | RW | GPIO48 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO47 | RW | GPIO47 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO46 | RW | GPIO46 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO45 | RW | GPIO45 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO44 | RW | GPIO44 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO43 | RW | GPIO43 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO42 | RW | GPIO42 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO41 | RW | GPIO41 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO40 | RW | GPIO40 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO39 | RW | GPIO39 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO38 | RW | GPIO38 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO37 | RW | GPIO37 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO36 | RW | GPIO36 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO35 | RW | GPIO35 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO34 | RW | GPIO34 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO33 | RW | GPIO33 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO32 | RW | GPIO32 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x4001031C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO63
0x0 |
MCUN1GPIO62
0x0 |
MCUN1GPIO61
0x0 |
MCUN1GPIO60
0x0 |
MCUN1GPIO59
0x0 |
MCUN1GPIO58
0x0 |
MCUN1GPIO57
0x0 |
MCUN1GPIO56
0x0 |
MCUN1GPIO55
0x0 |
MCUN1GPIO54
0x0 |
MCUN1GPIO53
0x0 |
MCUN1GPIO52
0x0 |
MCUN1GPIO51
0x0 |
MCUN1GPIO50
0x0 |
MCUN1GPIO49
0x0 |
MCUN1GPIO48
0x0 |
MCUN1GPIO47
0x0 |
MCUN1GPIO46
0x0 |
MCUN1GPIO45
0x0 |
MCUN1GPIO44
0x0 |
MCUN1GPIO43
0x0 |
MCUN1GPIO42
0x0 |
MCUN1GPIO41
0x0 |
MCUN1GPIO40
0x0 |
MCUN1GPIO39
0x0 |
MCUN1GPIO38
0x0 |
MCUN1GPIO37
0x0 |
MCUN1GPIO36
0x0 |
MCUN1GPIO35
0x0 |
MCUN1GPIO34
0x0 |
MCUN1GPIO33
0x0 |
MCUN1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO63 | RW | GPIO63 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO62 | RW | GPIO62 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO61 | RW | GPIO61 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO60 | RW | GPIO60 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO59 | RW | GPIO59 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO58 | RW | GPIO58 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO57 | RW | GPIO57 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO56 | RW | GPIO56 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO55 | RW | GPIO55 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO54 | RW | GPIO54 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO53 | RW | GPIO53 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO52 | RW | GPIO52 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO51 | RW | GPIO51 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO50 | RW | GPIO50 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO49 | RW | GPIO49 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO48 | RW | GPIO48 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO47 | RW | GPIO47 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO46 | RW | GPIO46 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO45 | RW | GPIO45 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO44 | RW | GPIO44 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO43 | RW | GPIO43 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO42 | RW | GPIO42 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO41 | RW | GPIO41 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO40 | RW | GPIO40 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO39 | RW | GPIO39 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO38 | RW | GPIO38 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO37 | RW | GPIO37 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO36 | RW | GPIO36 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO35 | RW | GPIO35 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO34 | RW | GPIO34 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO33 | RW | GPIO33 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO32 | RW | GPIO32 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010320 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO95
0x0 |
MCUN1GPIO94
0x0 |
MCUN1GPIO93
0x0 |
MCUN1GPIO92
0x0 |
MCUN1GPIO91
0x0 |
MCUN1GPIO90
0x0 |
MCUN1GPIO89
0x0 |
MCUN1GPIO88
0x0 |
MCUN1GPIO87
0x0 |
MCUN1GPIO86
0x0 |
MCUN1GPIO85
0x0 |
MCUN1GPIO84
0x0 |
MCUN1GPIO83
0x0 |
MCUN1GPIO82
0x0 |
MCUN1GPIO81
0x0 |
MCUN1GPIO80
0x0 |
MCUN1GPIO79
0x0 |
MCUN1GPIO78
0x0 |
MCUN1GPIO77
0x0 |
MCUN1GPIO76
0x0 |
MCUN1GPIO75
0x0 |
MCUN1GPIO74
0x0 |
MCUN1GPIO73
0x0 |
MCUN1GPIO72
0x0 |
MCUN1GPIO71
0x0 |
MCUN1GPIO70
0x0 |
MCUN1GPIO69
0x0 |
MCUN1GPIO68
0x0 |
MCUN1GPIO67
0x0 |
MCUN1GPIO66
0x0 |
MCUN1GPIO65
0x0 |
MCUN1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO95 | RW | GPIO95 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO94 | RW | GPIO94 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO93 | RW | GPIO93 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO92 | RW | GPIO92 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO91 | RW | GPIO91 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO90 | RW | GPIO90 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO89 | RW | GPIO89 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO88 | RW | GPIO88 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO87 | RW | GPIO87 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO86 | RW | GPIO86 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO85 | RW | GPIO85 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO84 | RW | GPIO84 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO83 | RW | GPIO83 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO82 | RW | GPIO82 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO81 | RW | GPIO81 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO80 | RW | GPIO80 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO79 | RW | GPIO79 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO78 | RW | GPIO78 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO77 | RW | GPIO77 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO76 | RW | GPIO76 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO75 | RW | GPIO75 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO74 | RW | GPIO74 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO73 | RW | GPIO73 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO72 | RW | GPIO72 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO71 | RW | GPIO71 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO70 | RW | GPIO70 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO69 | RW | GPIO69 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO68 | RW | GPIO68 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO67 | RW | GPIO67 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO66 | RW | GPIO66 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO65 | RW | GPIO65 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO64 | RW | GPIO64 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010324 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO95
0x0 |
MCUN1GPIO94
0x0 |
MCUN1GPIO93
0x0 |
MCUN1GPIO92
0x0 |
MCUN1GPIO91
0x0 |
MCUN1GPIO90
0x0 |
MCUN1GPIO89
0x0 |
MCUN1GPIO88
0x0 |
MCUN1GPIO87
0x0 |
MCUN1GPIO86
0x0 |
MCUN1GPIO85
0x0 |
MCUN1GPIO84
0x0 |
MCUN1GPIO83
0x0 |
MCUN1GPIO82
0x0 |
MCUN1GPIO81
0x0 |
MCUN1GPIO80
0x0 |
MCUN1GPIO79
0x0 |
MCUN1GPIO78
0x0 |
MCUN1GPIO77
0x0 |
MCUN1GPIO76
0x0 |
MCUN1GPIO75
0x0 |
MCUN1GPIO74
0x0 |
MCUN1GPIO73
0x0 |
MCUN1GPIO72
0x0 |
MCUN1GPIO71
0x0 |
MCUN1GPIO70
0x0 |
MCUN1GPIO69
0x0 |
MCUN1GPIO68
0x0 |
MCUN1GPIO67
0x0 |
MCUN1GPIO66
0x0 |
MCUN1GPIO65
0x0 |
MCUN1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO95 | RW | GPIO95 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO94 | RW | GPIO94 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO93 | RW | GPIO93 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO92 | RW | GPIO92 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO91 | RW | GPIO91 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO90 | RW | GPIO90 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO89 | RW | GPIO89 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO88 | RW | GPIO88 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO87 | RW | GPIO87 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO86 | RW | GPIO86 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO85 | RW | GPIO85 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO84 | RW | GPIO84 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO83 | RW | GPIO83 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO82 | RW | GPIO82 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO81 | RW | GPIO81 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO80 | RW | GPIO80 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO79 | RW | GPIO79 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO78 | RW | GPIO78 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO77 | RW | GPIO77 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO76 | RW | GPIO76 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO75 | RW | GPIO75 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO74 | RW | GPIO74 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO73 | RW | GPIO73 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO72 | RW | GPIO72 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO71 | RW | GPIO71 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO70 | RW | GPIO70 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO69 | RW | GPIO69 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO68 | RW | GPIO68 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO67 | RW | GPIO67 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO66 | RW | GPIO66 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO65 | RW | GPIO65 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO64 | RW | GPIO64 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010328 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO95
0x0 |
MCUN1GPIO94
0x0 |
MCUN1GPIO93
0x0 |
MCUN1GPIO92
0x0 |
MCUN1GPIO91
0x0 |
MCUN1GPIO90
0x0 |
MCUN1GPIO89
0x0 |
MCUN1GPIO88
0x0 |
MCUN1GPIO87
0x0 |
MCUN1GPIO86
0x0 |
MCUN1GPIO85
0x0 |
MCUN1GPIO84
0x0 |
MCUN1GPIO83
0x0 |
MCUN1GPIO82
0x0 |
MCUN1GPIO81
0x0 |
MCUN1GPIO80
0x0 |
MCUN1GPIO79
0x0 |
MCUN1GPIO78
0x0 |
MCUN1GPIO77
0x0 |
MCUN1GPIO76
0x0 |
MCUN1GPIO75
0x0 |
MCUN1GPIO74
0x0 |
MCUN1GPIO73
0x0 |
MCUN1GPIO72
0x0 |
MCUN1GPIO71
0x0 |
MCUN1GPIO70
0x0 |
MCUN1GPIO69
0x0 |
MCUN1GPIO68
0x0 |
MCUN1GPIO67
0x0 |
MCUN1GPIO66
0x0 |
MCUN1GPIO65
0x0 |
MCUN1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO95 | RW | GPIO95 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO94 | RW | GPIO94 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO93 | RW | GPIO93 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO92 | RW | GPIO92 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO91 | RW | GPIO91 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO90 | RW | GPIO90 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO89 | RW | GPIO89 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO88 | RW | GPIO88 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO87 | RW | GPIO87 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO86 | RW | GPIO86 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO85 | RW | GPIO85 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO84 | RW | GPIO84 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO83 | RW | GPIO83 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO82 | RW | GPIO82 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO81 | RW | GPIO81 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO80 | RW | GPIO80 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO79 | RW | GPIO79 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO78 | RW | GPIO78 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO77 | RW | GPIO77 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO76 | RW | GPIO76 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO75 | RW | GPIO75 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO74 | RW | GPIO74 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO73 | RW | GPIO73 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO72 | RW | GPIO72 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO71 | RW | GPIO71 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO70 | RW | GPIO70 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO69 | RW | GPIO69 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO68 | RW | GPIO68 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO67 | RW | GPIO67 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO66 | RW | GPIO66 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO65 | RW | GPIO65 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO64 | RW | GPIO64 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x4001032C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO95
0x0 |
MCUN1GPIO94
0x0 |
MCUN1GPIO93
0x0 |
MCUN1GPIO92
0x0 |
MCUN1GPIO91
0x0 |
MCUN1GPIO90
0x0 |
MCUN1GPIO89
0x0 |
MCUN1GPIO88
0x0 |
MCUN1GPIO87
0x0 |
MCUN1GPIO86
0x0 |
MCUN1GPIO85
0x0 |
MCUN1GPIO84
0x0 |
MCUN1GPIO83
0x0 |
MCUN1GPIO82
0x0 |
MCUN1GPIO81
0x0 |
MCUN1GPIO80
0x0 |
MCUN1GPIO79
0x0 |
MCUN1GPIO78
0x0 |
MCUN1GPIO77
0x0 |
MCUN1GPIO76
0x0 |
MCUN1GPIO75
0x0 |
MCUN1GPIO74
0x0 |
MCUN1GPIO73
0x0 |
MCUN1GPIO72
0x0 |
MCUN1GPIO71
0x0 |
MCUN1GPIO70
0x0 |
MCUN1GPIO69
0x0 |
MCUN1GPIO68
0x0 |
MCUN1GPIO67
0x0 |
MCUN1GPIO66
0x0 |
MCUN1GPIO65
0x0 |
MCUN1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO95 | RW | GPIO95 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO94 | RW | GPIO94 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO93 | RW | GPIO93 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO92 | RW | GPIO92 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO91 | RW | GPIO91 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO90 | RW | GPIO90 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO89 | RW | GPIO89 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO88 | RW | GPIO88 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO87 | RW | GPIO87 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO86 | RW | GPIO86 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO85 | RW | GPIO85 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO84 | RW | GPIO84 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO83 | RW | GPIO83 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO82 | RW | GPIO82 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO81 | RW | GPIO81 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO80 | RW | GPIO80 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO79 | RW | GPIO79 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO78 | RW | GPIO78 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO77 | RW | GPIO77 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO76 | RW | GPIO76 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO75 | RW | GPIO75 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO74 | RW | GPIO74 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO73 | RW | GPIO73 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO72 | RW | GPIO72 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO71 | RW | GPIO71 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO70 | RW | GPIO70 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO69 | RW | GPIO69 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO68 | RW | GPIO68 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO67 | RW | GPIO67 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO66 | RW | GPIO66 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO65 | RW | GPIO65 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO64 | RW | GPIO64 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010330 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO127
0x0 |
MCUN1GPIO126
0x0 |
MCUN1GPIO125
0x0 |
MCUN1GPIO124
0x0 |
MCUN1GPIO123
0x0 |
MCUN1GPIO122
0x0 |
MCUN1GPIO121
0x0 |
MCUN1GPIO120
0x0 |
MCUN1GPIO119
0x0 |
MCUN1GPIO118
0x0 |
MCUN1GPIO117
0x0 |
MCUN1GPIO116
0x0 |
MCUN1GPIO115
0x0 |
MCUN1GPIO114
0x0 |
MCUN1GPIO113
0x0 |
MCUN1GPIO112
0x0 |
MCUN1GPIO111
0x0 |
MCUN1GPIO110
0x0 |
MCUN1GPIO109
0x0 |
MCUN1GPIO108
0x0 |
MCUN1GPIO107
0x0 |
MCUN1GPIO106
0x0 |
MCUN1GPIO105
0x0 |
MCUN1GPIO104
0x0 |
MCUN1GPIO103
0x0 |
MCUN1GPIO102
0x0 |
MCUN1GPIO101
0x0 |
MCUN1GPIO100
0x0 |
MCUN1GPIO99
0x0 |
MCUN1GPIO98
0x0 |
MCUN1GPIO97
0x0 |
MCUN1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO127 | RW | GPIO127 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO126 | RW | GPIO126 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO125 | RW | GPIO125 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO124 | RW | GPIO124 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO123 | RW | GPIO123 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO122 | RW | GPIO122 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO121 | RW | GPIO121 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO120 | RW | GPIO120 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO119 | RW | GPIO119 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO118 | RW | GPIO118 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO117 | RW | GPIO117 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO116 | RW | GPIO116 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO115 | RW | GPIO115 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO114 | RW | GPIO114 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO113 | RW | GPIO113 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO112 | RW | GPIO112 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO111 | RW | GPIO111 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO110 | RW | GPIO110 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO109 | RW | GPIO109 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO108 | RW | GPIO108 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO107 | RW | GPIO107 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO106 | RW | GPIO106 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO105 | RW | GPIO105 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO104 | RW | GPIO104 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO103 | RW | GPIO103 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO102 | RW | GPIO102 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO101 | RW | GPIO101 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO100 | RW | GPIO100 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO99 | RW | GPIO99 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO98 | RW | GPIO98 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO97 | RW | GPIO97 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO96 | RW | GPIO96 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010334 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO127
0x0 |
MCUN1GPIO126
0x0 |
MCUN1GPIO125
0x0 |
MCUN1GPIO124
0x0 |
MCUN1GPIO123
0x0 |
MCUN1GPIO122
0x0 |
MCUN1GPIO121
0x0 |
MCUN1GPIO120
0x0 |
MCUN1GPIO119
0x0 |
MCUN1GPIO118
0x0 |
MCUN1GPIO117
0x0 |
MCUN1GPIO116
0x0 |
MCUN1GPIO115
0x0 |
MCUN1GPIO114
0x0 |
MCUN1GPIO113
0x0 |
MCUN1GPIO112
0x0 |
MCUN1GPIO111
0x0 |
MCUN1GPIO110
0x0 |
MCUN1GPIO109
0x0 |
MCUN1GPIO108
0x0 |
MCUN1GPIO107
0x0 |
MCUN1GPIO106
0x0 |
MCUN1GPIO105
0x0 |
MCUN1GPIO104
0x0 |
MCUN1GPIO103
0x0 |
MCUN1GPIO102
0x0 |
MCUN1GPIO101
0x0 |
MCUN1GPIO100
0x0 |
MCUN1GPIO99
0x0 |
MCUN1GPIO98
0x0 |
MCUN1GPIO97
0x0 |
MCUN1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO127 | RW | GPIO127 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO126 | RW | GPIO126 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO125 | RW | GPIO125 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO124 | RW | GPIO124 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO123 | RW | GPIO123 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO122 | RW | GPIO122 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO121 | RW | GPIO121 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO120 | RW | GPIO120 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO119 | RW | GPIO119 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO118 | RW | GPIO118 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO117 | RW | GPIO117 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO116 | RW | GPIO116 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO115 | RW | GPIO115 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO114 | RW | GPIO114 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO113 | RW | GPIO113 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO112 | RW | GPIO112 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO111 | RW | GPIO111 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO110 | RW | GPIO110 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO109 | RW | GPIO109 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO108 | RW | GPIO108 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO107 | RW | GPIO107 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO106 | RW | GPIO106 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO105 | RW | GPIO105 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO104 | RW | GPIO104 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO103 | RW | GPIO103 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO102 | RW | GPIO102 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO101 | RW | GPIO101 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO100 | RW | GPIO100 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO99 | RW | GPIO99 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO98 | RW | GPIO98 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO97 | RW | GPIO97 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO96 | RW | GPIO96 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010338 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO127
0x0 |
MCUN1GPIO126
0x0 |
MCUN1GPIO125
0x0 |
MCUN1GPIO124
0x0 |
MCUN1GPIO123
0x0 |
MCUN1GPIO122
0x0 |
MCUN1GPIO121
0x0 |
MCUN1GPIO120
0x0 |
MCUN1GPIO119
0x0 |
MCUN1GPIO118
0x0 |
MCUN1GPIO117
0x0 |
MCUN1GPIO116
0x0 |
MCUN1GPIO115
0x0 |
MCUN1GPIO114
0x0 |
MCUN1GPIO113
0x0 |
MCUN1GPIO112
0x0 |
MCUN1GPIO111
0x0 |
MCUN1GPIO110
0x0 |
MCUN1GPIO109
0x0 |
MCUN1GPIO108
0x0 |
MCUN1GPIO107
0x0 |
MCUN1GPIO106
0x0 |
MCUN1GPIO105
0x0 |
MCUN1GPIO104
0x0 |
MCUN1GPIO103
0x0 |
MCUN1GPIO102
0x0 |
MCUN1GPIO101
0x0 |
MCUN1GPIO100
0x0 |
MCUN1GPIO99
0x0 |
MCUN1GPIO98
0x0 |
MCUN1GPIO97
0x0 |
MCUN1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO127 | RW | GPIO127 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO126 | RW | GPIO126 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO125 | RW | GPIO125 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO124 | RW | GPIO124 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO123 | RW | GPIO123 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO122 | RW | GPIO122 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO121 | RW | GPIO121 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO120 | RW | GPIO120 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO119 | RW | GPIO119 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO118 | RW | GPIO118 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO117 | RW | GPIO117 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO116 | RW | GPIO116 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO115 | RW | GPIO115 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO114 | RW | GPIO114 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO113 | RW | GPIO113 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO112 | RW | GPIO112 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO111 | RW | GPIO111 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO110 | RW | GPIO110 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO109 | RW | GPIO109 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO108 | RW | GPIO108 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO107 | RW | GPIO107 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO106 | RW | GPIO106 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO105 | RW | GPIO105 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO104 | RW | GPIO104 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO103 | RW | GPIO103 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO102 | RW | GPIO102 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO101 | RW | GPIO101 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO100 | RW | GPIO100 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO99 | RW | GPIO99 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO98 | RW | GPIO98 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO97 | RW | GPIO97 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO96 | RW | GPIO96 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x4001033C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCUN1GPIO127
0x0 |
MCUN1GPIO126
0x0 |
MCUN1GPIO125
0x0 |
MCUN1GPIO124
0x0 |
MCUN1GPIO123
0x0 |
MCUN1GPIO122
0x0 |
MCUN1GPIO121
0x0 |
MCUN1GPIO120
0x0 |
MCUN1GPIO119
0x0 |
MCUN1GPIO118
0x0 |
MCUN1GPIO117
0x0 |
MCUN1GPIO116
0x0 |
MCUN1GPIO115
0x0 |
MCUN1GPIO114
0x0 |
MCUN1GPIO113
0x0 |
MCUN1GPIO112
0x0 |
MCUN1GPIO111
0x0 |
MCUN1GPIO110
0x0 |
MCUN1GPIO109
0x0 |
MCUN1GPIO108
0x0 |
MCUN1GPIO107
0x0 |
MCUN1GPIO106
0x0 |
MCUN1GPIO105
0x0 |
MCUN1GPIO104
0x0 |
MCUN1GPIO103
0x0 |
MCUN1GPIO102
0x0 |
MCUN1GPIO101
0x0 |
MCUN1GPIO100
0x0 |
MCUN1GPIO99
0x0 |
MCUN1GPIO98
0x0 |
MCUN1GPIO97
0x0 |
MCUN1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | MCUN1GPIO127 | RW | GPIO127 MCU N1-priority interrupt. |
| 30 | MCUN1GPIO126 | RW | GPIO126 MCU N1-priority interrupt. |
| 29 | MCUN1GPIO125 | RW | GPIO125 MCU N1-priority interrupt. |
| 28 | MCUN1GPIO124 | RW | GPIO124 MCU N1-priority interrupt. |
| 27 | MCUN1GPIO123 | RW | GPIO123 MCU N1-priority interrupt. |
| 26 | MCUN1GPIO122 | RW | GPIO122 MCU N1-priority interrupt. |
| 25 | MCUN1GPIO121 | RW | GPIO121 MCU N1-priority interrupt. |
| 24 | MCUN1GPIO120 | RW | GPIO120 MCU N1-priority interrupt. |
| 23 | MCUN1GPIO119 | RW | GPIO119 MCU N1-priority interrupt. |
| 22 | MCUN1GPIO118 | RW | GPIO118 MCU N1-priority interrupt. |
| 21 | MCUN1GPIO117 | RW | GPIO117 MCU N1-priority interrupt. |
| 20 | MCUN1GPIO116 | RW | GPIO116 MCU N1-priority interrupt. |
| 19 | MCUN1GPIO115 | RW | GPIO115 MCU N1-priority interrupt. |
| 18 | MCUN1GPIO114 | RW | GPIO114 MCU N1-priority interrupt. |
| 17 | MCUN1GPIO113 | RW | GPIO113 MCU N1-priority interrupt. |
| 16 | MCUN1GPIO112 | RW | GPIO112 MCU N1-priority interrupt. |
| 15 | MCUN1GPIO111 | RW | GPIO111 MCU N1-priority interrupt. |
| 14 | MCUN1GPIO110 | RW | GPIO110 MCU N1-priority interrupt. |
| 13 | MCUN1GPIO109 | RW | GPIO109 MCU N1-priority interrupt. |
| 12 | MCUN1GPIO108 | RW | GPIO108 MCU N1-priority interrupt. |
| 11 | MCUN1GPIO107 | RW | GPIO107 MCU N1-priority interrupt. |
| 10 | MCUN1GPIO106 | RW | GPIO106 MCU N1-priority interrupt. |
| 9 | MCUN1GPIO105 | RW | GPIO105 MCU N1-priority interrupt. |
| 8 | MCUN1GPIO104 | RW | GPIO104 MCU N1-priority interrupt. |
| 7 | MCUN1GPIO103 | RW | GPIO103 MCU N1-priority interrupt. |
| 6 | MCUN1GPIO102 | RW | GPIO102 MCU N1-priority interrupt. |
| 5 | MCUN1GPIO101 | RW | GPIO101 MCU N1-priority interrupt. |
| 4 | MCUN1GPIO100 | RW | GPIO100 MCU N1-priority interrupt. |
| 3 | MCUN1GPIO99 | RW | GPIO99 MCU N1-priority interrupt. |
| 2 | MCUN1GPIO98 | RW | GPIO98 MCU N1-priority interrupt. |
| 1 | MCUN1GPIO97 | RW | GPIO97 MCU N1-priority interrupt. |
| 0 | MCUN1GPIO96 | RW | GPIO96 MCU N1-priority interrupt. |
| Instance 0 Address: | 0x40010340 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO31
0x0 |
DSP0N0GPIO30
0x0 |
DSP0N0GPIO29
0x0 |
DSP0N0GPIO28
0x0 |
DSP0N0GPIO27
0x0 |
DSP0N0GPIO26
0x0 |
DSP0N0GPIO25
0x0 |
DSP0N0GPIO24
0x0 |
DSP0N0GPIO23
0x0 |
DSP0N0GPIO22
0x0 |
DSP0N0GPIO21
0x0 |
DSP0N0GPIO20
0x0 |
DSP0N0GPIO19
0x0 |
DSP0N0GPIO18
0x0 |
DSP0N0GPIO17
0x0 |
DSP0N0GPIO16
0x0 |
DSP0N0GPIO15
0x0 |
DSP0N0GPIO14
0x0 |
DSP0N0GPIO13
0x0 |
DSP0N0GPIO12
0x0 |
DSP0N0GPIO11
0x0 |
DSP0N0GPIO10
0x0 |
DSP0N0GPIO9
0x0 |
DSP0N0GPIO8
0x0 |
DSP0N0GPIO7
0x0 |
DSP0N0GPIO6
0x0 |
DSP0N0GPIO5
0x0 |
DSP0N0GPIO4
0x0 |
DSP0N0GPIO3
0x0 |
DSP0N0GPIO2
0x0 |
DSP0N0GPIO1
0x0 |
DSP0N0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO31 | RW | GPIO31 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO30 | RW | GPIO30 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO29 | RW | GPIO29 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO28 | RW | GPIO28 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO27 | RW | GPIO27 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO26 | RW | GPIO26 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO25 | RW | GPIO25 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO24 | RW | GPIO24 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO23 | RW | GPIO23 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO22 | RW | GPIO22 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO21 | RW | GPIO21 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO20 | RW | GPIO20 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO19 | RW | GPIO19 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO18 | RW | GPIO18 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO17 | RW | GPIO17 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO16 | RW | GPIO16 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO15 | RW | GPIO15 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO14 | RW | GPIO14 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO13 | RW | GPIO13 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO12 | RW | GPIO12 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO11 | RW | GPIO11 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO10 | RW | GPIO10 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO9 | RW | GPIO9 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO8 | RW | GPIO8 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO7 | RW | GPIO7 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO6 | RW | GPIO6 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO5 | RW | GPIO5 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO4 | RW | GPIO4 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO3 | RW | GPIO3 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO2 | RW | GPIO2 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO1 | RW | GPIO1 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO0 | RW | GPIO0 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010344 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO31
0x0 |
DSP0N0GPIO30
0x0 |
DSP0N0GPIO29
0x0 |
DSP0N0GPIO28
0x0 |
DSP0N0GPIO27
0x0 |
DSP0N0GPIO26
0x0 |
DSP0N0GPIO25
0x0 |
DSP0N0GPIO24
0x0 |
DSP0N0GPIO23
0x0 |
DSP0N0GPIO22
0x0 |
DSP0N0GPIO21
0x0 |
DSP0N0GPIO20
0x0 |
DSP0N0GPIO19
0x0 |
DSP0N0GPIO18
0x0 |
DSP0N0GPIO17
0x0 |
DSP0N0GPIO16
0x0 |
DSP0N0GPIO15
0x0 |
DSP0N0GPIO14
0x0 |
DSP0N0GPIO13
0x0 |
DSP0N0GPIO12
0x0 |
DSP0N0GPIO11
0x0 |
DSP0N0GPIO10
0x0 |
DSP0N0GPIO9
0x0 |
DSP0N0GPIO8
0x0 |
DSP0N0GPIO7
0x0 |
DSP0N0GPIO6
0x0 |
DSP0N0GPIO5
0x0 |
DSP0N0GPIO4
0x0 |
DSP0N0GPIO3
0x0 |
DSP0N0GPIO2
0x0 |
DSP0N0GPIO1
0x0 |
DSP0N0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO31 | RW | GPIO31 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO30 | RW | GPIO30 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO29 | RW | GPIO29 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO28 | RW | GPIO28 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO27 | RW | GPIO27 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO26 | RW | GPIO26 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO25 | RW | GPIO25 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO24 | RW | GPIO24 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO23 | RW | GPIO23 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO22 | RW | GPIO22 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO21 | RW | GPIO21 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO20 | RW | GPIO20 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO19 | RW | GPIO19 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO18 | RW | GPIO18 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO17 | RW | GPIO17 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO16 | RW | GPIO16 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO15 | RW | GPIO15 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO14 | RW | GPIO14 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO13 | RW | GPIO13 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO12 | RW | GPIO12 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO11 | RW | GPIO11 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO10 | RW | GPIO10 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO9 | RW | GPIO9 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO8 | RW | GPIO8 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO7 | RW | GPIO7 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO6 | RW | GPIO6 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO5 | RW | GPIO5 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO4 | RW | GPIO4 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO3 | RW | GPIO3 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO2 | RW | GPIO2 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO1 | RW | GPIO1 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO0 | RW | GPIO0 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010348 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO31
0x0 |
DSP0N0GPIO30
0x0 |
DSP0N0GPIO29
0x0 |
DSP0N0GPIO28
0x0 |
DSP0N0GPIO27
0x0 |
DSP0N0GPIO26
0x0 |
DSP0N0GPIO25
0x0 |
DSP0N0GPIO24
0x0 |
DSP0N0GPIO23
0x0 |
DSP0N0GPIO22
0x0 |
DSP0N0GPIO21
0x0 |
DSP0N0GPIO20
0x0 |
DSP0N0GPIO19
0x0 |
DSP0N0GPIO18
0x0 |
DSP0N0GPIO17
0x0 |
DSP0N0GPIO16
0x0 |
DSP0N0GPIO15
0x0 |
DSP0N0GPIO14
0x0 |
DSP0N0GPIO13
0x0 |
DSP0N0GPIO12
0x0 |
DSP0N0GPIO11
0x0 |
DSP0N0GPIO10
0x0 |
DSP0N0GPIO9
0x0 |
DSP0N0GPIO8
0x0 |
DSP0N0GPIO7
0x0 |
DSP0N0GPIO6
0x0 |
DSP0N0GPIO5
0x0 |
DSP0N0GPIO4
0x0 |
DSP0N0GPIO3
0x0 |
DSP0N0GPIO2
0x0 |
DSP0N0GPIO1
0x0 |
DSP0N0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO31 | RW | GPIO31 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO30 | RW | GPIO30 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO29 | RW | GPIO29 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO28 | RW | GPIO28 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO27 | RW | GPIO27 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO26 | RW | GPIO26 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO25 | RW | GPIO25 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO24 | RW | GPIO24 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO23 | RW | GPIO23 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO22 | RW | GPIO22 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO21 | RW | GPIO21 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO20 | RW | GPIO20 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO19 | RW | GPIO19 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO18 | RW | GPIO18 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO17 | RW | GPIO17 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO16 | RW | GPIO16 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO15 | RW | GPIO15 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO14 | RW | GPIO14 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO13 | RW | GPIO13 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO12 | RW | GPIO12 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO11 | RW | GPIO11 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO10 | RW | GPIO10 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO9 | RW | GPIO9 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO8 | RW | GPIO8 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO7 | RW | GPIO7 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO6 | RW | GPIO6 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO5 | RW | GPIO5 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO4 | RW | GPIO4 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO3 | RW | GPIO3 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO2 | RW | GPIO2 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO1 | RW | GPIO1 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO0 | RW | GPIO0 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x4001034C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO31
0x0 |
DSP0N0GPIO30
0x0 |
DSP0N0GPIO29
0x0 |
DSP0N0GPIO28
0x0 |
DSP0N0GPIO27
0x0 |
DSP0N0GPIO26
0x0 |
DSP0N0GPIO25
0x0 |
DSP0N0GPIO24
0x0 |
DSP0N0GPIO23
0x0 |
DSP0N0GPIO22
0x0 |
DSP0N0GPIO21
0x0 |
DSP0N0GPIO20
0x0 |
DSP0N0GPIO19
0x0 |
DSP0N0GPIO18
0x0 |
DSP0N0GPIO17
0x0 |
DSP0N0GPIO16
0x0 |
DSP0N0GPIO15
0x0 |
DSP0N0GPIO14
0x0 |
DSP0N0GPIO13
0x0 |
DSP0N0GPIO12
0x0 |
DSP0N0GPIO11
0x0 |
DSP0N0GPIO10
0x0 |
DSP0N0GPIO9
0x0 |
DSP0N0GPIO8
0x0 |
DSP0N0GPIO7
0x0 |
DSP0N0GPIO6
0x0 |
DSP0N0GPIO5
0x0 |
DSP0N0GPIO4
0x0 |
DSP0N0GPIO3
0x0 |
DSP0N0GPIO2
0x0 |
DSP0N0GPIO1
0x0 |
DSP0N0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO31 | RW | GPIO31 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO30 | RW | GPIO30 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO29 | RW | GPIO29 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO28 | RW | GPIO28 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO27 | RW | GPIO27 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO26 | RW | GPIO26 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO25 | RW | GPIO25 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO24 | RW | GPIO24 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO23 | RW | GPIO23 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO22 | RW | GPIO22 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO21 | RW | GPIO21 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO20 | RW | GPIO20 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO19 | RW | GPIO19 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO18 | RW | GPIO18 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO17 | RW | GPIO17 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO16 | RW | GPIO16 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO15 | RW | GPIO15 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO14 | RW | GPIO14 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO13 | RW | GPIO13 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO12 | RW | GPIO12 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO11 | RW | GPIO11 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO10 | RW | GPIO10 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO9 | RW | GPIO9 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO8 | RW | GPIO8 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO7 | RW | GPIO7 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO6 | RW | GPIO6 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO5 | RW | GPIO5 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO4 | RW | GPIO4 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO3 | RW | GPIO3 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO2 | RW | GPIO2 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO1 | RW | GPIO1 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO0 | RW | GPIO0 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010350 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO63
0x0 |
DSP0N0GPIO62
0x0 |
DSP0N0GPIO61
0x0 |
DSP0N0GPIO60
0x0 |
DSP0N0GPIO59
0x0 |
DSP0N0GPIO58
0x0 |
DSP0N0GPIO57
0x0 |
DSP0N0GPIO56
0x0 |
DSP0N0GPIO55
0x0 |
DSP0N0GPIO54
0x0 |
DSP0N0GPIO53
0x0 |
DSP0N0GPIO52
0x0 |
DSP0N0GPIO51
0x0 |
DSP0N0GPIO50
0x0 |
DSP0N0GPIO49
0x0 |
DSP0N0GPIO48
0x0 |
DSP0N0GPIO47
0x0 |
DSP0N0GPIO46
0x0 |
DSP0N0GPIO45
0x0 |
DSP0N0GPIO44
0x0 |
DSP0N0GPIO43
0x0 |
DSP0N0GPIO42
0x0 |
DSP0N0GPIO41
0x0 |
DSP0N0GPIO40
0x0 |
DSP0N0GPIO39
0x0 |
DSP0N0GPIO38
0x0 |
DSP0N0GPIO37
0x0 |
DSP0N0GPIO36
0x0 |
DSP0N0GPIO35
0x0 |
DSP0N0GPIO34
0x0 |
DSP0N0GPIO33
0x0 |
DSP0N0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO63 | RW | GPIO63 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO62 | RW | GPIO62 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO61 | RW | GPIO61 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO60 | RW | GPIO60 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO59 | RW | GPIO59 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO58 | RW | GPIO58 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO57 | RW | GPIO57 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO56 | RW | GPIO56 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO55 | RW | GPIO55 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO54 | RW | GPIO54 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO53 | RW | GPIO53 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO52 | RW | GPIO52 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO51 | RW | GPIO51 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO50 | RW | GPIO50 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO49 | RW | GPIO49 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO48 | RW | GPIO48 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO47 | RW | GPIO47 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO46 | RW | GPIO46 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO45 | RW | GPIO45 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO44 | RW | GPIO44 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO43 | RW | GPIO43 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO42 | RW | GPIO42 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO41 | RW | GPIO41 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO40 | RW | GPIO40 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO39 | RW | GPIO39 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO38 | RW | GPIO38 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO37 | RW | GPIO37 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO36 | RW | GPIO36 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO35 | RW | GPIO35 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO34 | RW | GPIO34 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO33 | RW | GPIO33 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO32 | RW | GPIO32 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010354 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO63
0x0 |
DSP0N0GPIO62
0x0 |
DSP0N0GPIO61
0x0 |
DSP0N0GPIO60
0x0 |
DSP0N0GPIO59
0x0 |
DSP0N0GPIO58
0x0 |
DSP0N0GPIO57
0x0 |
DSP0N0GPIO56
0x0 |
DSP0N0GPIO55
0x0 |
DSP0N0GPIO54
0x0 |
DSP0N0GPIO53
0x0 |
DSP0N0GPIO52
0x0 |
DSP0N0GPIO51
0x0 |
DSP0N0GPIO50
0x0 |
DSP0N0GPIO49
0x0 |
DSP0N0GPIO48
0x0 |
DSP0N0GPIO47
0x0 |
DSP0N0GPIO46
0x0 |
DSP0N0GPIO45
0x0 |
DSP0N0GPIO44
0x0 |
DSP0N0GPIO43
0x0 |
DSP0N0GPIO42
0x0 |
DSP0N0GPIO41
0x0 |
DSP0N0GPIO40
0x0 |
DSP0N0GPIO39
0x0 |
DSP0N0GPIO38
0x0 |
DSP0N0GPIO37
0x0 |
DSP0N0GPIO36
0x0 |
DSP0N0GPIO35
0x0 |
DSP0N0GPIO34
0x0 |
DSP0N0GPIO33
0x0 |
DSP0N0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO63 | RW | GPIO63 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO62 | RW | GPIO62 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO61 | RW | GPIO61 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO60 | RW | GPIO60 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO59 | RW | GPIO59 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO58 | RW | GPIO58 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO57 | RW | GPIO57 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO56 | RW | GPIO56 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO55 | RW | GPIO55 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO54 | RW | GPIO54 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO53 | RW | GPIO53 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO52 | RW | GPIO52 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO51 | RW | GPIO51 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO50 | RW | GPIO50 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO49 | RW | GPIO49 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO48 | RW | GPIO48 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO47 | RW | GPIO47 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO46 | RW | GPIO46 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO45 | RW | GPIO45 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO44 | RW | GPIO44 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO43 | RW | GPIO43 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO42 | RW | GPIO42 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO41 | RW | GPIO41 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO40 | RW | GPIO40 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO39 | RW | GPIO39 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO38 | RW | GPIO38 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO37 | RW | GPIO37 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO36 | RW | GPIO36 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO35 | RW | GPIO35 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO34 | RW | GPIO34 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO33 | RW | GPIO33 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO32 | RW | GPIO32 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010358 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO63
0x0 |
DSP0N0GPIO62
0x0 |
DSP0N0GPIO61
0x0 |
DSP0N0GPIO60
0x0 |
DSP0N0GPIO59
0x0 |
DSP0N0GPIO58
0x0 |
DSP0N0GPIO57
0x0 |
DSP0N0GPIO56
0x0 |
DSP0N0GPIO55
0x0 |
DSP0N0GPIO54
0x0 |
DSP0N0GPIO53
0x0 |
DSP0N0GPIO52
0x0 |
DSP0N0GPIO51
0x0 |
DSP0N0GPIO50
0x0 |
DSP0N0GPIO49
0x0 |
DSP0N0GPIO48
0x0 |
DSP0N0GPIO47
0x0 |
DSP0N0GPIO46
0x0 |
DSP0N0GPIO45
0x0 |
DSP0N0GPIO44
0x0 |
DSP0N0GPIO43
0x0 |
DSP0N0GPIO42
0x0 |
DSP0N0GPIO41
0x0 |
DSP0N0GPIO40
0x0 |
DSP0N0GPIO39
0x0 |
DSP0N0GPIO38
0x0 |
DSP0N0GPIO37
0x0 |
DSP0N0GPIO36
0x0 |
DSP0N0GPIO35
0x0 |
DSP0N0GPIO34
0x0 |
DSP0N0GPIO33
0x0 |
DSP0N0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO63 | RW | GPIO63 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO62 | RW | GPIO62 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO61 | RW | GPIO61 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO60 | RW | GPIO60 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO59 | RW | GPIO59 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO58 | RW | GPIO58 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO57 | RW | GPIO57 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO56 | RW | GPIO56 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO55 | RW | GPIO55 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO54 | RW | GPIO54 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO53 | RW | GPIO53 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO52 | RW | GPIO52 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO51 | RW | GPIO51 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO50 | RW | GPIO50 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO49 | RW | GPIO49 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO48 | RW | GPIO48 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO47 | RW | GPIO47 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO46 | RW | GPIO46 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO45 | RW | GPIO45 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO44 | RW | GPIO44 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO43 | RW | GPIO43 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO42 | RW | GPIO42 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO41 | RW | GPIO41 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO40 | RW | GPIO40 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO39 | RW | GPIO39 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO38 | RW | GPIO38 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO37 | RW | GPIO37 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO36 | RW | GPIO36 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO35 | RW | GPIO35 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO34 | RW | GPIO34 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO33 | RW | GPIO33 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO32 | RW | GPIO32 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x4001035C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO63
0x0 |
DSP0N0GPIO62
0x0 |
DSP0N0GPIO61
0x0 |
DSP0N0GPIO60
0x0 |
DSP0N0GPIO59
0x0 |
DSP0N0GPIO58
0x0 |
DSP0N0GPIO57
0x0 |
DSP0N0GPIO56
0x0 |
DSP0N0GPIO55
0x0 |
DSP0N0GPIO54
0x0 |
DSP0N0GPIO53
0x0 |
DSP0N0GPIO52
0x0 |
DSP0N0GPIO51
0x0 |
DSP0N0GPIO50
0x0 |
DSP0N0GPIO49
0x0 |
DSP0N0GPIO48
0x0 |
DSP0N0GPIO47
0x0 |
DSP0N0GPIO46
0x0 |
DSP0N0GPIO45
0x0 |
DSP0N0GPIO44
0x0 |
DSP0N0GPIO43
0x0 |
DSP0N0GPIO42
0x0 |
DSP0N0GPIO41
0x0 |
DSP0N0GPIO40
0x0 |
DSP0N0GPIO39
0x0 |
DSP0N0GPIO38
0x0 |
DSP0N0GPIO37
0x0 |
DSP0N0GPIO36
0x0 |
DSP0N0GPIO35
0x0 |
DSP0N0GPIO34
0x0 |
DSP0N0GPIO33
0x0 |
DSP0N0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO63 | RW | GPIO63 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO62 | RW | GPIO62 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO61 | RW | GPIO61 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO60 | RW | GPIO60 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO59 | RW | GPIO59 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO58 | RW | GPIO58 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO57 | RW | GPIO57 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO56 | RW | GPIO56 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO55 | RW | GPIO55 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO54 | RW | GPIO54 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO53 | RW | GPIO53 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO52 | RW | GPIO52 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO51 | RW | GPIO51 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO50 | RW | GPIO50 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO49 | RW | GPIO49 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO48 | RW | GPIO48 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO47 | RW | GPIO47 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO46 | RW | GPIO46 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO45 | RW | GPIO45 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO44 | RW | GPIO44 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO43 | RW | GPIO43 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO42 | RW | GPIO42 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO41 | RW | GPIO41 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO40 | RW | GPIO40 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO39 | RW | GPIO39 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO38 | RW | GPIO38 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO37 | RW | GPIO37 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO36 | RW | GPIO36 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO35 | RW | GPIO35 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO34 | RW | GPIO34 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO33 | RW | GPIO33 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO32 | RW | GPIO32 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010360 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO95
0x0 |
DSP0N0GPIO94
0x0 |
DSP0N0GPIO93
0x0 |
DSP0N0GPIO92
0x0 |
DSP0N0GPIO91
0x0 |
DSP0N0GPIO90
0x0 |
DSP0N0GPIO89
0x0 |
DSP0N0GPIO88
0x0 |
DSP0N0GPIO87
0x0 |
DSP0N0GPIO86
0x0 |
DSP0N0GPIO85
0x0 |
DSP0N0GPIO84
0x0 |
DSP0N0GPIO83
0x0 |
DSP0N0GPIO82
0x0 |
DSP0N0GPIO81
0x0 |
DSP0N0GPIO80
0x0 |
DSP0N0GPIO79
0x0 |
DSP0N0GPIO78
0x0 |
DSP0N0GPIO77
0x0 |
DSP0N0GPIO76
0x0 |
DSP0N0GPIO75
0x0 |
DSP0N0GPIO74
0x0 |
DSP0N0GPIO73
0x0 |
DSP0N0GPIO72
0x0 |
DSP0N0GPIO71
0x0 |
DSP0N0GPIO70
0x0 |
DSP0N0GPIO69
0x0 |
DSP0N0GPIO68
0x0 |
DSP0N0GPIO67
0x0 |
DSP0N0GPIO66
0x0 |
DSP0N0GPIO65
0x0 |
DSP0N0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO95 | RW | GPIO95 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO94 | RW | GPIO94 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO93 | RW | GPIO93 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO92 | RW | GPIO92 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO91 | RW | GPIO91 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO90 | RW | GPIO90 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO89 | RW | GPIO89 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO88 | RW | GPIO88 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO87 | RW | GPIO87 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO86 | RW | GPIO86 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO85 | RW | GPIO85 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO84 | RW | GPIO84 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO83 | RW | GPIO83 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO82 | RW | GPIO82 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO81 | RW | GPIO81 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO80 | RW | GPIO80 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO79 | RW | GPIO79 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO78 | RW | GPIO78 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO77 | RW | GPIO77 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO76 | RW | GPIO76 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO75 | RW | GPIO75 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO74 | RW | GPIO74 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO73 | RW | GPIO73 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO72 | RW | GPIO72 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO71 | RW | GPIO71 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO70 | RW | GPIO70 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO69 | RW | GPIO69 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO68 | RW | GPIO68 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO67 | RW | GPIO67 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO66 | RW | GPIO66 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO65 | RW | GPIO65 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO64 | RW | GPIO64 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010364 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO95
0x0 |
DSP0N0GPIO94
0x0 |
DSP0N0GPIO93
0x0 |
DSP0N0GPIO92
0x0 |
DSP0N0GPIO91
0x0 |
DSP0N0GPIO90
0x0 |
DSP0N0GPIO89
0x0 |
DSP0N0GPIO88
0x0 |
DSP0N0GPIO87
0x0 |
DSP0N0GPIO86
0x0 |
DSP0N0GPIO85
0x0 |
DSP0N0GPIO84
0x0 |
DSP0N0GPIO83
0x0 |
DSP0N0GPIO82
0x0 |
DSP0N0GPIO81
0x0 |
DSP0N0GPIO80
0x0 |
DSP0N0GPIO79
0x0 |
DSP0N0GPIO78
0x0 |
DSP0N0GPIO77
0x0 |
DSP0N0GPIO76
0x0 |
DSP0N0GPIO75
0x0 |
DSP0N0GPIO74
0x0 |
DSP0N0GPIO73
0x0 |
DSP0N0GPIO72
0x0 |
DSP0N0GPIO71
0x0 |
DSP0N0GPIO70
0x0 |
DSP0N0GPIO69
0x0 |
DSP0N0GPIO68
0x0 |
DSP0N0GPIO67
0x0 |
DSP0N0GPIO66
0x0 |
DSP0N0GPIO65
0x0 |
DSP0N0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO95 | RW | GPIO95 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO94 | RW | GPIO94 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO93 | RW | GPIO93 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO92 | RW | GPIO92 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO91 | RW | GPIO91 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO90 | RW | GPIO90 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO89 | RW | GPIO89 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO88 | RW | GPIO88 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO87 | RW | GPIO87 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO86 | RW | GPIO86 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO85 | RW | GPIO85 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO84 | RW | GPIO84 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO83 | RW | GPIO83 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO82 | RW | GPIO82 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO81 | RW | GPIO81 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO80 | RW | GPIO80 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO79 | RW | GPIO79 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO78 | RW | GPIO78 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO77 | RW | GPIO77 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO76 | RW | GPIO76 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO75 | RW | GPIO75 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO74 | RW | GPIO74 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO73 | RW | GPIO73 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO72 | RW | GPIO72 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO71 | RW | GPIO71 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO70 | RW | GPIO70 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO69 | RW | GPIO69 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO68 | RW | GPIO68 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO67 | RW | GPIO67 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO66 | RW | GPIO66 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO65 | RW | GPIO65 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO64 | RW | GPIO64 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010368 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO95
0x0 |
DSP0N0GPIO94
0x0 |
DSP0N0GPIO93
0x0 |
DSP0N0GPIO92
0x0 |
DSP0N0GPIO91
0x0 |
DSP0N0GPIO90
0x0 |
DSP0N0GPIO89
0x0 |
DSP0N0GPIO88
0x0 |
DSP0N0GPIO87
0x0 |
DSP0N0GPIO86
0x0 |
DSP0N0GPIO85
0x0 |
DSP0N0GPIO84
0x0 |
DSP0N0GPIO83
0x0 |
DSP0N0GPIO82
0x0 |
DSP0N0GPIO81
0x0 |
DSP0N0GPIO80
0x0 |
DSP0N0GPIO79
0x0 |
DSP0N0GPIO78
0x0 |
DSP0N0GPIO77
0x0 |
DSP0N0GPIO76
0x0 |
DSP0N0GPIO75
0x0 |
DSP0N0GPIO74
0x0 |
DSP0N0GPIO73
0x0 |
DSP0N0GPIO72
0x0 |
DSP0N0GPIO71
0x0 |
DSP0N0GPIO70
0x0 |
DSP0N0GPIO69
0x0 |
DSP0N0GPIO68
0x0 |
DSP0N0GPIO67
0x0 |
DSP0N0GPIO66
0x0 |
DSP0N0GPIO65
0x0 |
DSP0N0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO95 | RW | GPIO95 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO94 | RW | GPIO94 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO93 | RW | GPIO93 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO92 | RW | GPIO92 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO91 | RW | GPIO91 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO90 | RW | GPIO90 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO89 | RW | GPIO89 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO88 | RW | GPIO88 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO87 | RW | GPIO87 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO86 | RW | GPIO86 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO85 | RW | GPIO85 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO84 | RW | GPIO84 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO83 | RW | GPIO83 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO82 | RW | GPIO82 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO81 | RW | GPIO81 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO80 | RW | GPIO80 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO79 | RW | GPIO79 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO78 | RW | GPIO78 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO77 | RW | GPIO77 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO76 | RW | GPIO76 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO75 | RW | GPIO75 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO74 | RW | GPIO74 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO73 | RW | GPIO73 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO72 | RW | GPIO72 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO71 | RW | GPIO71 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO70 | RW | GPIO70 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO69 | RW | GPIO69 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO68 | RW | GPIO68 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO67 | RW | GPIO67 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO66 | RW | GPIO66 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO65 | RW | GPIO65 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO64 | RW | GPIO64 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x4001036C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO95
0x0 |
DSP0N0GPIO94
0x0 |
DSP0N0GPIO93
0x0 |
DSP0N0GPIO92
0x0 |
DSP0N0GPIO91
0x0 |
DSP0N0GPIO90
0x0 |
DSP0N0GPIO89
0x0 |
DSP0N0GPIO88
0x0 |
DSP0N0GPIO87
0x0 |
DSP0N0GPIO86
0x0 |
DSP0N0GPIO85
0x0 |
DSP0N0GPIO84
0x0 |
DSP0N0GPIO83
0x0 |
DSP0N0GPIO82
0x0 |
DSP0N0GPIO81
0x0 |
DSP0N0GPIO80
0x0 |
DSP0N0GPIO79
0x0 |
DSP0N0GPIO78
0x0 |
DSP0N0GPIO77
0x0 |
DSP0N0GPIO76
0x0 |
DSP0N0GPIO75
0x0 |
DSP0N0GPIO74
0x0 |
DSP0N0GPIO73
0x0 |
DSP0N0GPIO72
0x0 |
DSP0N0GPIO71
0x0 |
DSP0N0GPIO70
0x0 |
DSP0N0GPIO69
0x0 |
DSP0N0GPIO68
0x0 |
DSP0N0GPIO67
0x0 |
DSP0N0GPIO66
0x0 |
DSP0N0GPIO65
0x0 |
DSP0N0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO95 | RW | GPIO95 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO94 | RW | GPIO94 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO93 | RW | GPIO93 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO92 | RW | GPIO92 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO91 | RW | GPIO91 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO90 | RW | GPIO90 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO89 | RW | GPIO89 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO88 | RW | GPIO88 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO87 | RW | GPIO87 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO86 | RW | GPIO86 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO85 | RW | GPIO85 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO84 | RW | GPIO84 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO83 | RW | GPIO83 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO82 | RW | GPIO82 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO81 | RW | GPIO81 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO80 | RW | GPIO80 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO79 | RW | GPIO79 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO78 | RW | GPIO78 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO77 | RW | GPIO77 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO76 | RW | GPIO76 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO75 | RW | GPIO75 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO74 | RW | GPIO74 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO73 | RW | GPIO73 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO72 | RW | GPIO72 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO71 | RW | GPIO71 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO70 | RW | GPIO70 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO69 | RW | GPIO69 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO68 | RW | GPIO68 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO67 | RW | GPIO67 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO66 | RW | GPIO66 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO65 | RW | GPIO65 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO64 | RW | GPIO64 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010370 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO127
0x0 |
DSP0N0GPIO126
0x0 |
DSP0N0GPIO125
0x0 |
DSP0N0GPIO124
0x0 |
DSP0N0GPIO123
0x0 |
DSP0N0GPIO122
0x0 |
DSP0N0GPIO121
0x0 |
DSP0N0GPIO120
0x0 |
DSP0N0GPIO119
0x0 |
DSP0N0GPIO118
0x0 |
DSP0N0GPIO117
0x0 |
DSP0N0GPIO116
0x0 |
DSP0N0GPIO115
0x0 |
DSP0N0GPIO114
0x0 |
DSP0N0GPIO113
0x0 |
DSP0N0GPIO112
0x0 |
DSP0N0GPIO111
0x0 |
DSP0N0GPIO110
0x0 |
DSP0N0GPIO109
0x0 |
DSP0N0GPIO108
0x0 |
DSP0N0GPIO107
0x0 |
DSP0N0GPIO106
0x0 |
DSP0N0GPIO105
0x0 |
DSP0N0GPIO104
0x0 |
DSP0N0GPIO103
0x0 |
DSP0N0GPIO102
0x0 |
DSP0N0GPIO101
0x0 |
DSP0N0GPIO100
0x0 |
DSP0N0GPIO99
0x0 |
DSP0N0GPIO98
0x0 |
DSP0N0GPIO97
0x0 |
DSP0N0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO127 | RW | GPIO127 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO126 | RW | GPIO126 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO125 | RW | GPIO125 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO124 | RW | GPIO124 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO123 | RW | GPIO123 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO122 | RW | GPIO122 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO121 | RW | GPIO121 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO120 | RW | GPIO120 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO119 | RW | GPIO119 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO118 | RW | GPIO118 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO117 | RW | GPIO117 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO116 | RW | GPIO116 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO115 | RW | GPIO115 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO114 | RW | GPIO114 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO113 | RW | GPIO113 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO112 | RW | GPIO112 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO111 | RW | GPIO111 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO110 | RW | GPIO110 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO109 | RW | GPIO109 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO108 | RW | GPIO108 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO107 | RW | GPIO107 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO106 | RW | GPIO106 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO105 | RW | GPIO105 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO104 | RW | GPIO104 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO103 | RW | GPIO103 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO102 | RW | GPIO102 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO101 | RW | GPIO101 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO100 | RW | GPIO100 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO99 | RW | GPIO99 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO98 | RW | GPIO98 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO97 | RW | GPIO97 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO96 | RW | GPIO96 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010374 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO127
0x0 |
DSP0N0GPIO126
0x0 |
DSP0N0GPIO125
0x0 |
DSP0N0GPIO124
0x0 |
DSP0N0GPIO123
0x0 |
DSP0N0GPIO122
0x0 |
DSP0N0GPIO121
0x0 |
DSP0N0GPIO120
0x0 |
DSP0N0GPIO119
0x0 |
DSP0N0GPIO118
0x0 |
DSP0N0GPIO117
0x0 |
DSP0N0GPIO116
0x0 |
DSP0N0GPIO115
0x0 |
DSP0N0GPIO114
0x0 |
DSP0N0GPIO113
0x0 |
DSP0N0GPIO112
0x0 |
DSP0N0GPIO111
0x0 |
DSP0N0GPIO110
0x0 |
DSP0N0GPIO109
0x0 |
DSP0N0GPIO108
0x0 |
DSP0N0GPIO107
0x0 |
DSP0N0GPIO106
0x0 |
DSP0N0GPIO105
0x0 |
DSP0N0GPIO104
0x0 |
DSP0N0GPIO103
0x0 |
DSP0N0GPIO102
0x0 |
DSP0N0GPIO101
0x0 |
DSP0N0GPIO100
0x0 |
DSP0N0GPIO99
0x0 |
DSP0N0GPIO98
0x0 |
DSP0N0GPIO97
0x0 |
DSP0N0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO127 | RW | GPIO127 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO126 | RW | GPIO126 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO125 | RW | GPIO125 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO124 | RW | GPIO124 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO123 | RW | GPIO123 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO122 | RW | GPIO122 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO121 | RW | GPIO121 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO120 | RW | GPIO120 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO119 | RW | GPIO119 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO118 | RW | GPIO118 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO117 | RW | GPIO117 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO116 | RW | GPIO116 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO115 | RW | GPIO115 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO114 | RW | GPIO114 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO113 | RW | GPIO113 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO112 | RW | GPIO112 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO111 | RW | GPIO111 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO110 | RW | GPIO110 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO109 | RW | GPIO109 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO108 | RW | GPIO108 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO107 | RW | GPIO107 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO106 | RW | GPIO106 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO105 | RW | GPIO105 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO104 | RW | GPIO104 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO103 | RW | GPIO103 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO102 | RW | GPIO102 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO101 | RW | GPIO101 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO100 | RW | GPIO100 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO99 | RW | GPIO99 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO98 | RW | GPIO98 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO97 | RW | GPIO97 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO96 | RW | GPIO96 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010378 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO127
0x0 |
DSP0N0GPIO126
0x0 |
DSP0N0GPIO125
0x0 |
DSP0N0GPIO124
0x0 |
DSP0N0GPIO123
0x0 |
DSP0N0GPIO122
0x0 |
DSP0N0GPIO121
0x0 |
DSP0N0GPIO120
0x0 |
DSP0N0GPIO119
0x0 |
DSP0N0GPIO118
0x0 |
DSP0N0GPIO117
0x0 |
DSP0N0GPIO116
0x0 |
DSP0N0GPIO115
0x0 |
DSP0N0GPIO114
0x0 |
DSP0N0GPIO113
0x0 |
DSP0N0GPIO112
0x0 |
DSP0N0GPIO111
0x0 |
DSP0N0GPIO110
0x0 |
DSP0N0GPIO109
0x0 |
DSP0N0GPIO108
0x0 |
DSP0N0GPIO107
0x0 |
DSP0N0GPIO106
0x0 |
DSP0N0GPIO105
0x0 |
DSP0N0GPIO104
0x0 |
DSP0N0GPIO103
0x0 |
DSP0N0GPIO102
0x0 |
DSP0N0GPIO101
0x0 |
DSP0N0GPIO100
0x0 |
DSP0N0GPIO99
0x0 |
DSP0N0GPIO98
0x0 |
DSP0N0GPIO97
0x0 |
DSP0N0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO127 | RW | GPIO127 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO126 | RW | GPIO126 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO125 | RW | GPIO125 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO124 | RW | GPIO124 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO123 | RW | GPIO123 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO122 | RW | GPIO122 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO121 | RW | GPIO121 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO120 | RW | GPIO120 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO119 | RW | GPIO119 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO118 | RW | GPIO118 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO117 | RW | GPIO117 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO116 | RW | GPIO116 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO115 | RW | GPIO115 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO114 | RW | GPIO114 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO113 | RW | GPIO113 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO112 | RW | GPIO112 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO111 | RW | GPIO111 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO110 | RW | GPIO110 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO109 | RW | GPIO109 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO108 | RW | GPIO108 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO107 | RW | GPIO107 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO106 | RW | GPIO106 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO105 | RW | GPIO105 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO104 | RW | GPIO104 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO103 | RW | GPIO103 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO102 | RW | GPIO102 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO101 | RW | GPIO101 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO100 | RW | GPIO100 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO99 | RW | GPIO99 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO98 | RW | GPIO98 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO97 | RW | GPIO97 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO96 | RW | GPIO96 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x4001037C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N0GPIO127
0x0 |
DSP0N0GPIO126
0x0 |
DSP0N0GPIO125
0x0 |
DSP0N0GPIO124
0x0 |
DSP0N0GPIO123
0x0 |
DSP0N0GPIO122
0x0 |
DSP0N0GPIO121
0x0 |
DSP0N0GPIO120
0x0 |
DSP0N0GPIO119
0x0 |
DSP0N0GPIO118
0x0 |
DSP0N0GPIO117
0x0 |
DSP0N0GPIO116
0x0 |
DSP0N0GPIO115
0x0 |
DSP0N0GPIO114
0x0 |
DSP0N0GPIO113
0x0 |
DSP0N0GPIO112
0x0 |
DSP0N0GPIO111
0x0 |
DSP0N0GPIO110
0x0 |
DSP0N0GPIO109
0x0 |
DSP0N0GPIO108
0x0 |
DSP0N0GPIO107
0x0 |
DSP0N0GPIO106
0x0 |
DSP0N0GPIO105
0x0 |
DSP0N0GPIO104
0x0 |
DSP0N0GPIO103
0x0 |
DSP0N0GPIO102
0x0 |
DSP0N0GPIO101
0x0 |
DSP0N0GPIO100
0x0 |
DSP0N0GPIO99
0x0 |
DSP0N0GPIO98
0x0 |
DSP0N0GPIO97
0x0 |
DSP0N0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N0GPIO127 | RW | GPIO127 DSP0 N0-priority interrupt. |
| 30 | DSP0N0GPIO126 | RW | GPIO126 DSP0 N0-priority interrupt. |
| 29 | DSP0N0GPIO125 | RW | GPIO125 DSP0 N0-priority interrupt. |
| 28 | DSP0N0GPIO124 | RW | GPIO124 DSP0 N0-priority interrupt. |
| 27 | DSP0N0GPIO123 | RW | GPIO123 DSP0 N0-priority interrupt. |
| 26 | DSP0N0GPIO122 | RW | GPIO122 DSP0 N0-priority interrupt. |
| 25 | DSP0N0GPIO121 | RW | GPIO121 DSP0 N0-priority interrupt. |
| 24 | DSP0N0GPIO120 | RW | GPIO120 DSP0 N0-priority interrupt. |
| 23 | DSP0N0GPIO119 | RW | GPIO119 DSP0 N0-priority interrupt. |
| 22 | DSP0N0GPIO118 | RW | GPIO118 DSP0 N0-priority interrupt. |
| 21 | DSP0N0GPIO117 | RW | GPIO117 DSP0 N0-priority interrupt. |
| 20 | DSP0N0GPIO116 | RW | GPIO116 DSP0 N0-priority interrupt. |
| 19 | DSP0N0GPIO115 | RW | GPIO115 DSP0 N0-priority interrupt. |
| 18 | DSP0N0GPIO114 | RW | GPIO114 DSP0 N0-priority interrupt. |
| 17 | DSP0N0GPIO113 | RW | GPIO113 DSP0 N0-priority interrupt. |
| 16 | DSP0N0GPIO112 | RW | GPIO112 DSP0 N0-priority interrupt. |
| 15 | DSP0N0GPIO111 | RW | GPIO111 DSP0 N0-priority interrupt. |
| 14 | DSP0N0GPIO110 | RW | GPIO110 DSP0 N0-priority interrupt. |
| 13 | DSP0N0GPIO109 | RW | GPIO109 DSP0 N0-priority interrupt. |
| 12 | DSP0N0GPIO108 | RW | GPIO108 DSP0 N0-priority interrupt. |
| 11 | DSP0N0GPIO107 | RW | GPIO107 DSP0 N0-priority interrupt. |
| 10 | DSP0N0GPIO106 | RW | GPIO106 DSP0 N0-priority interrupt. |
| 9 | DSP0N0GPIO105 | RW | GPIO105 DSP0 N0-priority interrupt. |
| 8 | DSP0N0GPIO104 | RW | GPIO104 DSP0 N0-priority interrupt. |
| 7 | DSP0N0GPIO103 | RW | GPIO103 DSP0 N0-priority interrupt. |
| 6 | DSP0N0GPIO102 | RW | GPIO102 DSP0 N0-priority interrupt. |
| 5 | DSP0N0GPIO101 | RW | GPIO101 DSP0 N0-priority interrupt. |
| 4 | DSP0N0GPIO100 | RW | GPIO100 DSP0 N0-priority interrupt. |
| 3 | DSP0N0GPIO99 | RW | GPIO99 DSP0 N0-priority interrupt. |
| 2 | DSP0N0GPIO98 | RW | GPIO98 DSP0 N0-priority interrupt. |
| 1 | DSP0N0GPIO97 | RW | GPIO97 DSP0 N0-priority interrupt. |
| 0 | DSP0N0GPIO96 | RW | GPIO96 DSP0 N0-priority interrupt. |
| Instance 0 Address: | 0x40010380 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO31
0x0 |
DSP0N1GPIO30
0x0 |
DSP0N1GPIO29
0x0 |
DSP0N1GPIO28
0x0 |
DSP0N1GPIO27
0x0 |
DSP0N1GPIO26
0x0 |
DSP0N1GPIO25
0x0 |
DSP0N1GPIO24
0x0 |
DSP0N1GPIO23
0x0 |
DSP0N1GPIO22
0x0 |
DSP0N1GPIO21
0x0 |
DSP0N1GPIO20
0x0 |
DSP0N1GPIO19
0x0 |
DSP0N1GPIO18
0x0 |
DSP0N1GPIO17
0x0 |
DSP0N1GPIO16
0x0 |
DSP0N1GPIO15
0x0 |
DSP0N1GPIO14
0x0 |
DSP0N1GPIO13
0x0 |
DSP0N1GPIO12
0x0 |
DSP0N1GPIO11
0x0 |
DSP0N1GPIO10
0x0 |
DSP0N1GPIO9
0x0 |
DSP0N1GPIO8
0x0 |
DSP0N1GPIO7
0x0 |
DSP0N1GPIO6
0x0 |
DSP0N1GPIO5
0x0 |
DSP0N1GPIO4
0x0 |
DSP0N1GPIO3
0x0 |
DSP0N1GPIO2
0x0 |
DSP0N1GPIO1
0x0 |
DSP0N1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO31 | RW | GPIO31 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO30 | RW | GPIO30 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO29 | RW | GPIO29 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO28 | RW | GPIO28 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO27 | RW | GPIO27 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO26 | RW | GPIO26 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO25 | RW | GPIO25 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO24 | RW | GPIO24 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO23 | RW | GPIO23 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO22 | RW | GPIO22 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO21 | RW | GPIO21 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO20 | RW | GPIO20 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO19 | RW | GPIO19 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO18 | RW | GPIO18 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO17 | RW | GPIO17 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO16 | RW | GPIO16 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO15 | RW | GPIO15 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO14 | RW | GPIO14 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO13 | RW | GPIO13 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO12 | RW | GPIO12 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO11 | RW | GPIO11 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO10 | RW | GPIO10 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO9 | RW | GPIO9 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO8 | RW | GPIO8 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO7 | RW | GPIO7 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO6 | RW | GPIO6 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO5 | RW | GPIO5 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO4 | RW | GPIO4 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO3 | RW | GPIO3 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO2 | RW | GPIO2 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO1 | RW | GPIO1 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO0 | RW | GPIO0 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x40010384 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO31
0x0 |
DSP0N1GPIO30
0x0 |
DSP0N1GPIO29
0x0 |
DSP0N1GPIO28
0x0 |
DSP0N1GPIO27
0x0 |
DSP0N1GPIO26
0x0 |
DSP0N1GPIO25
0x0 |
DSP0N1GPIO24
0x0 |
DSP0N1GPIO23
0x0 |
DSP0N1GPIO22
0x0 |
DSP0N1GPIO21
0x0 |
DSP0N1GPIO20
0x0 |
DSP0N1GPIO19
0x0 |
DSP0N1GPIO18
0x0 |
DSP0N1GPIO17
0x0 |
DSP0N1GPIO16
0x0 |
DSP0N1GPIO15
0x0 |
DSP0N1GPIO14
0x0 |
DSP0N1GPIO13
0x0 |
DSP0N1GPIO12
0x0 |
DSP0N1GPIO11
0x0 |
DSP0N1GPIO10
0x0 |
DSP0N1GPIO9
0x0 |
DSP0N1GPIO8
0x0 |
DSP0N1GPIO7
0x0 |
DSP0N1GPIO6
0x0 |
DSP0N1GPIO5
0x0 |
DSP0N1GPIO4
0x0 |
DSP0N1GPIO3
0x0 |
DSP0N1GPIO2
0x0 |
DSP0N1GPIO1
0x0 |
DSP0N1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO31 | RW | GPIO31 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO30 | RW | GPIO30 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO29 | RW | GPIO29 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO28 | RW | GPIO28 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO27 | RW | GPIO27 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO26 | RW | GPIO26 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO25 | RW | GPIO25 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO24 | RW | GPIO24 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO23 | RW | GPIO23 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO22 | RW | GPIO22 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO21 | RW | GPIO21 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO20 | RW | GPIO20 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO19 | RW | GPIO19 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO18 | RW | GPIO18 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO17 | RW | GPIO17 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO16 | RW | GPIO16 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO15 | RW | GPIO15 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO14 | RW | GPIO14 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO13 | RW | GPIO13 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO12 | RW | GPIO12 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO11 | RW | GPIO11 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO10 | RW | GPIO10 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO9 | RW | GPIO9 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO8 | RW | GPIO8 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO7 | RW | GPIO7 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO6 | RW | GPIO6 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO5 | RW | GPIO5 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO4 | RW | GPIO4 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO3 | RW | GPIO3 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO2 | RW | GPIO2 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO1 | RW | GPIO1 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO0 | RW | GPIO0 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x40010388 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO31
0x0 |
DSP0N1GPIO30
0x0 |
DSP0N1GPIO29
0x0 |
DSP0N1GPIO28
0x0 |
DSP0N1GPIO27
0x0 |
DSP0N1GPIO26
0x0 |
DSP0N1GPIO25
0x0 |
DSP0N1GPIO24
0x0 |
DSP0N1GPIO23
0x0 |
DSP0N1GPIO22
0x0 |
DSP0N1GPIO21
0x0 |
DSP0N1GPIO20
0x0 |
DSP0N1GPIO19
0x0 |
DSP0N1GPIO18
0x0 |
DSP0N1GPIO17
0x0 |
DSP0N1GPIO16
0x0 |
DSP0N1GPIO15
0x0 |
DSP0N1GPIO14
0x0 |
DSP0N1GPIO13
0x0 |
DSP0N1GPIO12
0x0 |
DSP0N1GPIO11
0x0 |
DSP0N1GPIO10
0x0 |
DSP0N1GPIO9
0x0 |
DSP0N1GPIO8
0x0 |
DSP0N1GPIO7
0x0 |
DSP0N1GPIO6
0x0 |
DSP0N1GPIO5
0x0 |
DSP0N1GPIO4
0x0 |
DSP0N1GPIO3
0x0 |
DSP0N1GPIO2
0x0 |
DSP0N1GPIO1
0x0 |
DSP0N1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO31 | RW | GPIO31 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO30 | RW | GPIO30 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO29 | RW | GPIO29 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO28 | RW | GPIO28 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO27 | RW | GPIO27 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO26 | RW | GPIO26 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO25 | RW | GPIO25 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO24 | RW | GPIO24 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO23 | RW | GPIO23 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO22 | RW | GPIO22 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO21 | RW | GPIO21 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO20 | RW | GPIO20 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO19 | RW | GPIO19 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO18 | RW | GPIO18 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO17 | RW | GPIO17 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO16 | RW | GPIO16 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO15 | RW | GPIO15 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO14 | RW | GPIO14 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO13 | RW | GPIO13 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO12 | RW | GPIO12 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO11 | RW | GPIO11 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO10 | RW | GPIO10 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO9 | RW | GPIO9 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO8 | RW | GPIO8 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO7 | RW | GPIO7 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO6 | RW | GPIO6 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO5 | RW | GPIO5 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO4 | RW | GPIO4 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO3 | RW | GPIO3 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO2 | RW | GPIO2 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO1 | RW | GPIO1 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO0 | RW | GPIO0 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x4001038C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO31
0x0 |
DSP0N1GPIO30
0x0 |
DSP0N1GPIO29
0x0 |
DSP0N1GPIO28
0x0 |
DSP0N1GPIO27
0x0 |
DSP0N1GPIO26
0x0 |
DSP0N1GPIO25
0x0 |
DSP0N1GPIO24
0x0 |
DSP0N1GPIO23
0x0 |
DSP0N1GPIO22
0x0 |
DSP0N1GPIO21
0x0 |
DSP0N1GPIO20
0x0 |
DSP0N1GPIO19
0x0 |
DSP0N1GPIO18
0x0 |
DSP0N1GPIO17
0x0 |
DSP0N1GPIO16
0x0 |
DSP0N1GPIO15
0x0 |
DSP0N1GPIO14
0x0 |
DSP0N1GPIO13
0x0 |
DSP0N1GPIO12
0x0 |
DSP0N1GPIO11
0x0 |
DSP0N1GPIO10
0x0 |
DSP0N1GPIO9
0x0 |
DSP0N1GPIO8
0x0 |
DSP0N1GPIO7
0x0 |
DSP0N1GPIO6
0x0 |
DSP0N1GPIO5
0x0 |
DSP0N1GPIO4
0x0 |
DSP0N1GPIO3
0x0 |
DSP0N1GPIO2
0x0 |
DSP0N1GPIO1
0x0 |
DSP0N1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO31 | RW | GPIO31 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO30 | RW | GPIO30 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO29 | RW | GPIO29 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO28 | RW | GPIO28 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO27 | RW | GPIO27 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO26 | RW | GPIO26 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO25 | RW | GPIO25 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO24 | RW | GPIO24 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO23 | RW | GPIO23 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO22 | RW | GPIO22 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO21 | RW | GPIO21 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO20 | RW | GPIO20 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO19 | RW | GPIO19 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO18 | RW | GPIO18 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO17 | RW | GPIO17 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO16 | RW | GPIO16 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO15 | RW | GPIO15 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO14 | RW | GPIO14 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO13 | RW | GPIO13 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO12 | RW | GPIO12 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO11 | RW | GPIO11 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO10 | RW | GPIO10 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO9 | RW | GPIO9 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO8 | RW | GPIO8 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO7 | RW | GPIO7 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO6 | RW | GPIO6 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO5 | RW | GPIO5 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO4 | RW | GPIO4 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO3 | RW | GPIO3 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO2 | RW | GPIO2 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO1 | RW | GPIO1 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO0 | RW | GPIO0 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x40010390 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO63
0x0 |
DSP0N1GPIO62
0x0 |
DSP0N1GPIO61
0x0 |
DSP0N1GPIO60
0x0 |
DSP0N1GPIO59
0x0 |
DSP0N1GPIO58
0x0 |
DSP0N1GPIO57
0x0 |
DSP0N1GPIO56
0x0 |
DSP0N1GPIO55
0x0 |
DSP0N1GPIO54
0x0 |
DSP0N1GPIO53
0x0 |
DSP0N1GPIO52
0x0 |
DSP0N1GPIO51
0x0 |
DSP0N1GPIO50
0x0 |
DSP0N1GPIO49
0x0 |
DSP0N1GPIO48
0x0 |
DSP0N1GPIO47
0x0 |
DSP0N1GPIO46
0x0 |
DSP0N1GPIO45
0x0 |
DSP0N1GPIO44
0x0 |
DSP0N1GPIO43
0x0 |
DSP0N1GPIO42
0x0 |
DSP0N1GPIO41
0x0 |
DSP0N1GPIO40
0x0 |
DSP0N1GPIO39
0x0 |
DSP0N1GPIO38
0x0 |
DSP0N1GPIO37
0x0 |
DSP0N1GPIO36
0x0 |
DSP0N1GPIO35
0x0 |
DSP0N1GPIO34
0x0 |
DSP0N1GPIO33
0x0 |
DSP0N1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO63 | RW | GPIO63 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO62 | RW | GPIO62 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO61 | RW | GPIO61 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO60 | RW | GPIO60 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO59 | RW | GPIO59 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO58 | RW | GPIO58 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO57 | RW | GPIO57 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO56 | RW | GPIO56 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO55 | RW | GPIO55 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO54 | RW | GPIO54 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO53 | RW | GPIO53 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO52 | RW | GPIO52 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO51 | RW | GPIO51 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO50 | RW | GPIO50 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO49 | RW | GPIO49 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO48 | RW | GPIO48 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO47 | RW | GPIO47 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO46 | RW | GPIO46 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO45 | RW | GPIO45 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO44 | RW | GPIO44 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO43 | RW | GPIO43 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO42 | RW | GPIO42 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO41 | RW | GPIO41 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO40 | RW | GPIO40 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO39 | RW | GPIO39 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO38 | RW | GPIO38 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO37 | RW | GPIO37 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO36 | RW | GPIO36 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO35 | RW | GPIO35 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO34 | RW | GPIO34 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO33 | RW | GPIO33 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO32 | RW | GPIO32 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x40010394 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO63
0x0 |
DSP0N1GPIO62
0x0 |
DSP0N1GPIO61
0x0 |
DSP0N1GPIO60
0x0 |
DSP0N1GPIO59
0x0 |
DSP0N1GPIO58
0x0 |
DSP0N1GPIO57
0x0 |
DSP0N1GPIO56
0x0 |
DSP0N1GPIO55
0x0 |
DSP0N1GPIO54
0x0 |
DSP0N1GPIO53
0x0 |
DSP0N1GPIO52
0x0 |
DSP0N1GPIO51
0x0 |
DSP0N1GPIO50
0x0 |
DSP0N1GPIO49
0x0 |
DSP0N1GPIO48
0x0 |
DSP0N1GPIO47
0x0 |
DSP0N1GPIO46
0x0 |
DSP0N1GPIO45
0x0 |
DSP0N1GPIO44
0x0 |
DSP0N1GPIO43
0x0 |
DSP0N1GPIO42
0x0 |
DSP0N1GPIO41
0x0 |
DSP0N1GPIO40
0x0 |
DSP0N1GPIO39
0x0 |
DSP0N1GPIO38
0x0 |
DSP0N1GPIO37
0x0 |
DSP0N1GPIO36
0x0 |
DSP0N1GPIO35
0x0 |
DSP0N1GPIO34
0x0 |
DSP0N1GPIO33
0x0 |
DSP0N1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO63 | RW | GPIO63 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO62 | RW | GPIO62 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO61 | RW | GPIO61 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO60 | RW | GPIO60 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO59 | RW | GPIO59 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO58 | RW | GPIO58 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO57 | RW | GPIO57 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO56 | RW | GPIO56 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO55 | RW | GPIO55 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO54 | RW | GPIO54 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO53 | RW | GPIO53 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO52 | RW | GPIO52 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO51 | RW | GPIO51 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO50 | RW | GPIO50 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO49 | RW | GPIO49 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO48 | RW | GPIO48 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO47 | RW | GPIO47 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO46 | RW | GPIO46 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO45 | RW | GPIO45 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO44 | RW | GPIO44 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO43 | RW | GPIO43 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO42 | RW | GPIO42 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO41 | RW | GPIO41 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO40 | RW | GPIO40 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO39 | RW | GPIO39 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO38 | RW | GPIO38 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO37 | RW | GPIO37 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO36 | RW | GPIO36 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO35 | RW | GPIO35 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO34 | RW | GPIO34 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO33 | RW | GPIO33 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO32 | RW | GPIO32 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x40010398 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO63
0x0 |
DSP0N1GPIO62
0x0 |
DSP0N1GPIO61
0x0 |
DSP0N1GPIO60
0x0 |
DSP0N1GPIO59
0x0 |
DSP0N1GPIO58
0x0 |
DSP0N1GPIO57
0x0 |
DSP0N1GPIO56
0x0 |
DSP0N1GPIO55
0x0 |
DSP0N1GPIO54
0x0 |
DSP0N1GPIO53
0x0 |
DSP0N1GPIO52
0x0 |
DSP0N1GPIO51
0x0 |
DSP0N1GPIO50
0x0 |
DSP0N1GPIO49
0x0 |
DSP0N1GPIO48
0x0 |
DSP0N1GPIO47
0x0 |
DSP0N1GPIO46
0x0 |
DSP0N1GPIO45
0x0 |
DSP0N1GPIO44
0x0 |
DSP0N1GPIO43
0x0 |
DSP0N1GPIO42
0x0 |
DSP0N1GPIO41
0x0 |
DSP0N1GPIO40
0x0 |
DSP0N1GPIO39
0x0 |
DSP0N1GPIO38
0x0 |
DSP0N1GPIO37
0x0 |
DSP0N1GPIO36
0x0 |
DSP0N1GPIO35
0x0 |
DSP0N1GPIO34
0x0 |
DSP0N1GPIO33
0x0 |
DSP0N1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO63 | RW | GPIO63 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO62 | RW | GPIO62 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO61 | RW | GPIO61 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO60 | RW | GPIO60 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO59 | RW | GPIO59 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO58 | RW | GPIO58 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO57 | RW | GPIO57 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO56 | RW | GPIO56 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO55 | RW | GPIO55 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO54 | RW | GPIO54 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO53 | RW | GPIO53 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO52 | RW | GPIO52 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO51 | RW | GPIO51 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO50 | RW | GPIO50 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO49 | RW | GPIO49 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO48 | RW | GPIO48 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO47 | RW | GPIO47 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO46 | RW | GPIO46 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO45 | RW | GPIO45 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO44 | RW | GPIO44 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO43 | RW | GPIO43 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO42 | RW | GPIO42 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO41 | RW | GPIO41 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO40 | RW | GPIO40 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO39 | RW | GPIO39 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO38 | RW | GPIO38 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO37 | RW | GPIO37 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO36 | RW | GPIO36 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO35 | RW | GPIO35 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO34 | RW | GPIO34 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO33 | RW | GPIO33 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO32 | RW | GPIO32 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x4001039C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO63
0x0 |
DSP0N1GPIO62
0x0 |
DSP0N1GPIO61
0x0 |
DSP0N1GPIO60
0x0 |
DSP0N1GPIO59
0x0 |
DSP0N1GPIO58
0x0 |
DSP0N1GPIO57
0x0 |
DSP0N1GPIO56
0x0 |
DSP0N1GPIO55
0x0 |
DSP0N1GPIO54
0x0 |
DSP0N1GPIO53
0x0 |
DSP0N1GPIO52
0x0 |
DSP0N1GPIO51
0x0 |
DSP0N1GPIO50
0x0 |
DSP0N1GPIO49
0x0 |
DSP0N1GPIO48
0x0 |
DSP0N1GPIO47
0x0 |
DSP0N1GPIO46
0x0 |
DSP0N1GPIO45
0x0 |
DSP0N1GPIO44
0x0 |
DSP0N1GPIO43
0x0 |
DSP0N1GPIO42
0x0 |
DSP0N1GPIO41
0x0 |
DSP0N1GPIO40
0x0 |
DSP0N1GPIO39
0x0 |
DSP0N1GPIO38
0x0 |
DSP0N1GPIO37
0x0 |
DSP0N1GPIO36
0x0 |
DSP0N1GPIO35
0x0 |
DSP0N1GPIO34
0x0 |
DSP0N1GPIO33
0x0 |
DSP0N1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO63 | RW | GPIO63 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO62 | RW | GPIO62 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO61 | RW | GPIO61 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO60 | RW | GPIO60 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO59 | RW | GPIO59 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO58 | RW | GPIO58 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO57 | RW | GPIO57 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO56 | RW | GPIO56 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO55 | RW | GPIO55 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO54 | RW | GPIO54 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO53 | RW | GPIO53 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO52 | RW | GPIO52 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO51 | RW | GPIO51 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO50 | RW | GPIO50 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO49 | RW | GPIO49 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO48 | RW | GPIO48 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO47 | RW | GPIO47 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO46 | RW | GPIO46 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO45 | RW | GPIO45 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO44 | RW | GPIO44 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO43 | RW | GPIO43 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO42 | RW | GPIO42 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO41 | RW | GPIO41 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO40 | RW | GPIO40 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO39 | RW | GPIO39 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO38 | RW | GPIO38 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO37 | RW | GPIO37 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO36 | RW | GPIO36 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO35 | RW | GPIO35 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO34 | RW | GPIO34 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO33 | RW | GPIO33 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO32 | RW | GPIO32 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x400103A0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO95
0x0 |
DSP0N1GPIO94
0x0 |
DSP0N1GPIO93
0x0 |
DSP0N1GPIO92
0x0 |
DSP0N1GPIO91
0x0 |
DSP0N1GPIO90
0x0 |
DSP0N1GPIO89
0x0 |
DSP0N1GPIO88
0x0 |
DSP0N1GPIO87
0x0 |
DSP0N1GPIO86
0x0 |
DSP0N1GPIO85
0x0 |
DSP0N1GPIO84
0x0 |
DSP0N1GPIO83
0x0 |
DSP0N1GPIO82
0x0 |
DSP0N1GPIO81
0x0 |
DSP0N1GPIO80
0x0 |
DSP0N1GPIO79
0x0 |
DSP0N1GPIO78
0x0 |
DSP0N1GPIO77
0x0 |
DSP0N1GPIO76
0x0 |
DSP0N1GPIO75
0x0 |
DSP0N1GPIO74
0x0 |
DSP0N1GPIO73
0x0 |
DSP0N1GPIO72
0x0 |
DSP0N1GPIO71
0x0 |
DSP0N1GPIO70
0x0 |
DSP0N1GPIO69
0x0 |
DSP0N1GPIO68
0x0 |
DSP0N1GPIO67
0x0 |
DSP0N1GPIO66
0x0 |
DSP0N1GPIO65
0x0 |
DSP0N1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO95 | RW | GPIO95 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO94 | RW | GPIO94 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO93 | RW | GPIO93 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO92 | RW | GPIO92 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO91 | RW | GPIO91 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO90 | RW | GPIO90 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO89 | RW | GPIO89 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO88 | RW | GPIO88 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO87 | RW | GPIO87 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO86 | RW | GPIO86 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO85 | RW | GPIO85 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO84 | RW | GPIO84 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO83 | RW | GPIO83 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO82 | RW | GPIO82 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO81 | RW | GPIO81 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO80 | RW | GPIO80 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO79 | RW | GPIO79 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO78 | RW | GPIO78 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO77 | RW | GPIO77 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO76 | RW | GPIO76 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO75 | RW | GPIO75 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO74 | RW | GPIO74 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO73 | RW | GPIO73 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO72 | RW | GPIO72 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO71 | RW | GPIO71 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO70 | RW | GPIO70 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO69 | RW | GPIO69 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO68 | RW | GPIO68 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO67 | RW | GPIO67 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO66 | RW | GPIO66 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO65 | RW | GPIO65 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO64 | RW | GPIO64 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x400103A4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO95
0x0 |
DSP0N1GPIO94
0x0 |
DSP0N1GPIO93
0x0 |
DSP0N1GPIO92
0x0 |
DSP0N1GPIO91
0x0 |
DSP0N1GPIO90
0x0 |
DSP0N1GPIO89
0x0 |
DSP0N1GPIO88
0x0 |
DSP0N1GPIO87
0x0 |
DSP0N1GPIO86
0x0 |
DSP0N1GPIO85
0x0 |
DSP0N1GPIO84
0x0 |
DSP0N1GPIO83
0x0 |
DSP0N1GPIO82
0x0 |
DSP0N1GPIO81
0x0 |
DSP0N1GPIO80
0x0 |
DSP0N1GPIO79
0x0 |
DSP0N1GPIO78
0x0 |
DSP0N1GPIO77
0x0 |
DSP0N1GPIO76
0x0 |
DSP0N1GPIO75
0x0 |
DSP0N1GPIO74
0x0 |
DSP0N1GPIO73
0x0 |
DSP0N1GPIO72
0x0 |
DSP0N1GPIO71
0x0 |
DSP0N1GPIO70
0x0 |
DSP0N1GPIO69
0x0 |
DSP0N1GPIO68
0x0 |
DSP0N1GPIO67
0x0 |
DSP0N1GPIO66
0x0 |
DSP0N1GPIO65
0x0 |
DSP0N1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO95 | RW | GPIO95 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO94 | RW | GPIO94 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO93 | RW | GPIO93 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO92 | RW | GPIO92 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO91 | RW | GPIO91 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO90 | RW | GPIO90 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO89 | RW | GPIO89 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO88 | RW | GPIO88 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO87 | RW | GPIO87 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO86 | RW | GPIO86 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO85 | RW | GPIO85 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO84 | RW | GPIO84 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO83 | RW | GPIO83 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO82 | RW | GPIO82 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO81 | RW | GPIO81 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO80 | RW | GPIO80 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO79 | RW | GPIO79 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO78 | RW | GPIO78 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO77 | RW | GPIO77 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO76 | RW | GPIO76 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO75 | RW | GPIO75 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO74 | RW | GPIO74 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO73 | RW | GPIO73 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO72 | RW | GPIO72 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO71 | RW | GPIO71 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO70 | RW | GPIO70 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO69 | RW | GPIO69 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO68 | RW | GPIO68 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO67 | RW | GPIO67 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO66 | RW | GPIO66 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO65 | RW | GPIO65 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO64 | RW | GPIO64 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x400103A8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO95
0x0 |
DSP0N1GPIO94
0x0 |
DSP0N1GPIO93
0x0 |
DSP0N1GPIO92
0x0 |
DSP0N1GPIO91
0x0 |
DSP0N1GPIO90
0x0 |
DSP0N1GPIO89
0x0 |
DSP0N1GPIO88
0x0 |
DSP0N1GPIO87
0x0 |
DSP0N1GPIO86
0x0 |
DSP0N1GPIO85
0x0 |
DSP0N1GPIO84
0x0 |
DSP0N1GPIO83
0x0 |
DSP0N1GPIO82
0x0 |
DSP0N1GPIO81
0x0 |
DSP0N1GPIO80
0x0 |
DSP0N1GPIO79
0x0 |
DSP0N1GPIO78
0x0 |
DSP0N1GPIO77
0x0 |
DSP0N1GPIO76
0x0 |
DSP0N1GPIO75
0x0 |
DSP0N1GPIO74
0x0 |
DSP0N1GPIO73
0x0 |
DSP0N1GPIO72
0x0 |
DSP0N1GPIO71
0x0 |
DSP0N1GPIO70
0x0 |
DSP0N1GPIO69
0x0 |
DSP0N1GPIO68
0x0 |
DSP0N1GPIO67
0x0 |
DSP0N1GPIO66
0x0 |
DSP0N1GPIO65
0x0 |
DSP0N1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO95 | RW | GPIO95 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO94 | RW | GPIO94 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO93 | RW | GPIO93 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO92 | RW | GPIO92 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO91 | RW | GPIO91 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO90 | RW | GPIO90 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO89 | RW | GPIO89 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO88 | RW | GPIO88 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO87 | RW | GPIO87 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO86 | RW | GPIO86 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO85 | RW | GPIO85 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO84 | RW | GPIO84 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO83 | RW | GPIO83 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO82 | RW | GPIO82 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO81 | RW | GPIO81 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO80 | RW | GPIO80 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO79 | RW | GPIO79 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO78 | RW | GPIO78 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO77 | RW | GPIO77 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO76 | RW | GPIO76 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO75 | RW | GPIO75 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO74 | RW | GPIO74 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO73 | RW | GPIO73 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO72 | RW | GPIO72 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO71 | RW | GPIO71 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO70 | RW | GPIO70 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO69 | RW | GPIO69 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO68 | RW | GPIO68 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO67 | RW | GPIO67 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO66 | RW | GPIO66 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO65 | RW | GPIO65 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO64 | RW | GPIO64 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x400103AC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO95
0x0 |
DSP0N1GPIO94
0x0 |
DSP0N1GPIO93
0x0 |
DSP0N1GPIO92
0x0 |
DSP0N1GPIO91
0x0 |
DSP0N1GPIO90
0x0 |
DSP0N1GPIO89
0x0 |
DSP0N1GPIO88
0x0 |
DSP0N1GPIO87
0x0 |
DSP0N1GPIO86
0x0 |
DSP0N1GPIO85
0x0 |
DSP0N1GPIO84
0x0 |
DSP0N1GPIO83
0x0 |
DSP0N1GPIO82
0x0 |
DSP0N1GPIO81
0x0 |
DSP0N1GPIO80
0x0 |
DSP0N1GPIO79
0x0 |
DSP0N1GPIO78
0x0 |
DSP0N1GPIO77
0x0 |
DSP0N1GPIO76
0x0 |
DSP0N1GPIO75
0x0 |
DSP0N1GPIO74
0x0 |
DSP0N1GPIO73
0x0 |
DSP0N1GPIO72
0x0 |
DSP0N1GPIO71
0x0 |
DSP0N1GPIO70
0x0 |
DSP0N1GPIO69
0x0 |
DSP0N1GPIO68
0x0 |
DSP0N1GPIO67
0x0 |
DSP0N1GPIO66
0x0 |
DSP0N1GPIO65
0x0 |
DSP0N1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO95 | RW | GPIO95 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO94 | RW | GPIO94 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO93 | RW | GPIO93 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO92 | RW | GPIO92 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO91 | RW | GPIO91 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO90 | RW | GPIO90 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO89 | RW | GPIO89 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO88 | RW | GPIO88 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO87 | RW | GPIO87 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO86 | RW | GPIO86 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO85 | RW | GPIO85 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO84 | RW | GPIO84 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO83 | RW | GPIO83 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO82 | RW | GPIO82 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO81 | RW | GPIO81 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO80 | RW | GPIO80 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO79 | RW | GPIO79 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO78 | RW | GPIO78 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO77 | RW | GPIO77 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO76 | RW | GPIO76 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO75 | RW | GPIO75 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO74 | RW | GPIO74 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO73 | RW | GPIO73 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO72 | RW | GPIO72 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO71 | RW | GPIO71 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO70 | RW | GPIO70 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO69 | RW | GPIO69 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO68 | RW | GPIO68 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO67 | RW | GPIO67 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO66 | RW | GPIO66 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO65 | RW | GPIO65 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO64 | RW | GPIO64 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x400103B0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO127
0x0 |
DSP0N1GPIO126
0x0 |
DSP0N1GPIO125
0x0 |
DSP0N1GPIO124
0x0 |
DSP0N1GPIO123
0x0 |
DSP0N1GPIO122
0x0 |
DSP0N1GPIO121
0x0 |
DSP0N1GPIO120
0x0 |
DSP0N1GPIO119
0x0 |
DSP0N1GPIO118
0x0 |
DSP0N1GPIO117
0x0 |
DSP0N1GPIO116
0x0 |
DSP0N1GPIO115
0x0 |
DSP0N1GPIO114
0x0 |
DSP0N1GPIO113
0x0 |
DSP0N1GPIO112
0x0 |
DSP0N1GPIO111
0x0 |
DSP0N1GPIO110
0x0 |
DSP0N1GPIO109
0x0 |
DSP0N1GPIO108
0x0 |
DSP0N1GPIO107
0x0 |
DSP0N1GPIO106
0x0 |
DSP0N1GPIO105
0x0 |
DSP0N1GPIO104
0x0 |
DSP0N1GPIO103
0x0 |
DSP0N1GPIO102
0x0 |
DSP0N1GPIO101
0x0 |
DSP0N1GPIO100
0x0 |
DSP0N1GPIO99
0x0 |
DSP0N1GPIO98
0x0 |
DSP0N1GPIO97
0x0 |
DSP0N1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO127 | RW | GPIO127 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO126 | RW | GPIO126 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO125 | RW | GPIO125 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO124 | RW | GPIO124 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO123 | RW | GPIO123 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO122 | RW | GPIO122 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO121 | RW | GPIO121 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO120 | RW | GPIO120 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO119 | RW | GPIO119 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO118 | RW | GPIO118 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO117 | RW | GPIO117 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO116 | RW | GPIO116 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO115 | RW | GPIO115 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO114 | RW | GPIO114 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO113 | RW | GPIO113 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO112 | RW | GPIO112 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO111 | RW | GPIO111 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO110 | RW | GPIO110 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO109 | RW | GPIO109 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO108 | RW | GPIO108 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO107 | RW | GPIO107 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO106 | RW | GPIO106 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO105 | RW | GPIO105 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO104 | RW | GPIO104 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO103 | RW | GPIO103 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO102 | RW | GPIO102 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO101 | RW | GPIO101 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO100 | RW | GPIO100 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO99 | RW | GPIO99 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO98 | RW | GPIO98 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO97 | RW | GPIO97 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO96 | RW | GPIO96 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x400103B4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO127
0x0 |
DSP0N1GPIO126
0x0 |
DSP0N1GPIO125
0x0 |
DSP0N1GPIO124
0x0 |
DSP0N1GPIO123
0x0 |
DSP0N1GPIO122
0x0 |
DSP0N1GPIO121
0x0 |
DSP0N1GPIO120
0x0 |
DSP0N1GPIO119
0x0 |
DSP0N1GPIO118
0x0 |
DSP0N1GPIO117
0x0 |
DSP0N1GPIO116
0x0 |
DSP0N1GPIO115
0x0 |
DSP0N1GPIO114
0x0 |
DSP0N1GPIO113
0x0 |
DSP0N1GPIO112
0x0 |
DSP0N1GPIO111
0x0 |
DSP0N1GPIO110
0x0 |
DSP0N1GPIO109
0x0 |
DSP0N1GPIO108
0x0 |
DSP0N1GPIO107
0x0 |
DSP0N1GPIO106
0x0 |
DSP0N1GPIO105
0x0 |
DSP0N1GPIO104
0x0 |
DSP0N1GPIO103
0x0 |
DSP0N1GPIO102
0x0 |
DSP0N1GPIO101
0x0 |
DSP0N1GPIO100
0x0 |
DSP0N1GPIO99
0x0 |
DSP0N1GPIO98
0x0 |
DSP0N1GPIO97
0x0 |
DSP0N1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO127 | RW | GPIO127 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO126 | RW | GPIO126 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO125 | RW | GPIO125 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO124 | RW | GPIO124 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO123 | RW | GPIO123 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO122 | RW | GPIO122 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO121 | RW | GPIO121 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO120 | RW | GPIO120 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO119 | RW | GPIO119 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO118 | RW | GPIO118 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO117 | RW | GPIO117 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO116 | RW | GPIO116 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO115 | RW | GPIO115 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO114 | RW | GPIO114 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO113 | RW | GPIO113 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO112 | RW | GPIO112 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO111 | RW | GPIO111 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO110 | RW | GPIO110 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO109 | RW | GPIO109 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO108 | RW | GPIO108 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO107 | RW | GPIO107 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO106 | RW | GPIO106 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO105 | RW | GPIO105 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO104 | RW | GPIO104 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO103 | RW | GPIO103 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO102 | RW | GPIO102 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO101 | RW | GPIO101 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO100 | RW | GPIO100 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO99 | RW | GPIO99 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO98 | RW | GPIO98 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO97 | RW | GPIO97 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO96 | RW | GPIO96 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x400103B8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO127
0x0 |
DSP0N1GPIO126
0x0 |
DSP0N1GPIO125
0x0 |
DSP0N1GPIO124
0x0 |
DSP0N1GPIO123
0x0 |
DSP0N1GPIO122
0x0 |
DSP0N1GPIO121
0x0 |
DSP0N1GPIO120
0x0 |
DSP0N1GPIO119
0x0 |
DSP0N1GPIO118
0x0 |
DSP0N1GPIO117
0x0 |
DSP0N1GPIO116
0x0 |
DSP0N1GPIO115
0x0 |
DSP0N1GPIO114
0x0 |
DSP0N1GPIO113
0x0 |
DSP0N1GPIO112
0x0 |
DSP0N1GPIO111
0x0 |
DSP0N1GPIO110
0x0 |
DSP0N1GPIO109
0x0 |
DSP0N1GPIO108
0x0 |
DSP0N1GPIO107
0x0 |
DSP0N1GPIO106
0x0 |
DSP0N1GPIO105
0x0 |
DSP0N1GPIO104
0x0 |
DSP0N1GPIO103
0x0 |
DSP0N1GPIO102
0x0 |
DSP0N1GPIO101
0x0 |
DSP0N1GPIO100
0x0 |
DSP0N1GPIO99
0x0 |
DSP0N1GPIO98
0x0 |
DSP0N1GPIO97
0x0 |
DSP0N1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO127 | RW | GPIO127 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO126 | RW | GPIO126 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO125 | RW | GPIO125 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO124 | RW | GPIO124 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO123 | RW | GPIO123 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO122 | RW | GPIO122 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO121 | RW | GPIO121 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO120 | RW | GPIO120 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO119 | RW | GPIO119 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO118 | RW | GPIO118 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO117 | RW | GPIO117 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO116 | RW | GPIO116 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO115 | RW | GPIO115 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO114 | RW | GPIO114 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO113 | RW | GPIO113 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO112 | RW | GPIO112 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO111 | RW | GPIO111 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO110 | RW | GPIO110 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO109 | RW | GPIO109 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO108 | RW | GPIO108 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO107 | RW | GPIO107 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO106 | RW | GPIO106 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO105 | RW | GPIO105 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO104 | RW | GPIO104 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO103 | RW | GPIO103 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO102 | RW | GPIO102 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO101 | RW | GPIO101 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO100 | RW | GPIO100 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO99 | RW | GPIO99 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO98 | RW | GPIO98 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO97 | RW | GPIO97 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO96 | RW | GPIO96 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x400103BC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP0N1GPIO127
0x0 |
DSP0N1GPIO126
0x0 |
DSP0N1GPIO125
0x0 |
DSP0N1GPIO124
0x0 |
DSP0N1GPIO123
0x0 |
DSP0N1GPIO122
0x0 |
DSP0N1GPIO121
0x0 |
DSP0N1GPIO120
0x0 |
DSP0N1GPIO119
0x0 |
DSP0N1GPIO118
0x0 |
DSP0N1GPIO117
0x0 |
DSP0N1GPIO116
0x0 |
DSP0N1GPIO115
0x0 |
DSP0N1GPIO114
0x0 |
DSP0N1GPIO113
0x0 |
DSP0N1GPIO112
0x0 |
DSP0N1GPIO111
0x0 |
DSP0N1GPIO110
0x0 |
DSP0N1GPIO109
0x0 |
DSP0N1GPIO108
0x0 |
DSP0N1GPIO107
0x0 |
DSP0N1GPIO106
0x0 |
DSP0N1GPIO105
0x0 |
DSP0N1GPIO104
0x0 |
DSP0N1GPIO103
0x0 |
DSP0N1GPIO102
0x0 |
DSP0N1GPIO101
0x0 |
DSP0N1GPIO100
0x0 |
DSP0N1GPIO99
0x0 |
DSP0N1GPIO98
0x0 |
DSP0N1GPIO97
0x0 |
DSP0N1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP0N1GPIO127 | RW | GPIO127 DSP0 N1-priority interrupt. |
| 30 | DSP0N1GPIO126 | RW | GPIO126 DSP0 N1-priority interrupt. |
| 29 | DSP0N1GPIO125 | RW | GPIO125 DSP0 N1-priority interrupt. |
| 28 | DSP0N1GPIO124 | RW | GPIO124 DSP0 N1-priority interrupt. |
| 27 | DSP0N1GPIO123 | RW | GPIO123 DSP0 N1-priority interrupt. |
| 26 | DSP0N1GPIO122 | RW | GPIO122 DSP0 N1-priority interrupt. |
| 25 | DSP0N1GPIO121 | RW | GPIO121 DSP0 N1-priority interrupt. |
| 24 | DSP0N1GPIO120 | RW | GPIO120 DSP0 N1-priority interrupt. |
| 23 | DSP0N1GPIO119 | RW | GPIO119 DSP0 N1-priority interrupt. |
| 22 | DSP0N1GPIO118 | RW | GPIO118 DSP0 N1-priority interrupt. |
| 21 | DSP0N1GPIO117 | RW | GPIO117 DSP0 N1-priority interrupt. |
| 20 | DSP0N1GPIO116 | RW | GPIO116 DSP0 N1-priority interrupt. |
| 19 | DSP0N1GPIO115 | RW | GPIO115 DSP0 N1-priority interrupt. |
| 18 | DSP0N1GPIO114 | RW | GPIO114 DSP0 N1-priority interrupt. |
| 17 | DSP0N1GPIO113 | RW | GPIO113 DSP0 N1-priority interrupt. |
| 16 | DSP0N1GPIO112 | RW | GPIO112 DSP0 N1-priority interrupt. |
| 15 | DSP0N1GPIO111 | RW | GPIO111 DSP0 N1-priority interrupt. |
| 14 | DSP0N1GPIO110 | RW | GPIO110 DSP0 N1-priority interrupt. |
| 13 | DSP0N1GPIO109 | RW | GPIO109 DSP0 N1-priority interrupt. |
| 12 | DSP0N1GPIO108 | RW | GPIO108 DSP0 N1-priority interrupt. |
| 11 | DSP0N1GPIO107 | RW | GPIO107 DSP0 N1-priority interrupt. |
| 10 | DSP0N1GPIO106 | RW | GPIO106 DSP0 N1-priority interrupt. |
| 9 | DSP0N1GPIO105 | RW | GPIO105 DSP0 N1-priority interrupt. |
| 8 | DSP0N1GPIO104 | RW | GPIO104 DSP0 N1-priority interrupt. |
| 7 | DSP0N1GPIO103 | RW | GPIO103 DSP0 N1-priority interrupt. |
| 6 | DSP0N1GPIO102 | RW | GPIO102 DSP0 N1-priority interrupt. |
| 5 | DSP0N1GPIO101 | RW | GPIO101 DSP0 N1-priority interrupt. |
| 4 | DSP0N1GPIO100 | RW | GPIO100 DSP0 N1-priority interrupt. |
| 3 | DSP0N1GPIO99 | RW | GPIO99 DSP0 N1-priority interrupt. |
| 2 | DSP0N1GPIO98 | RW | GPIO98 DSP0 N1-priority interrupt. |
| 1 | DSP0N1GPIO97 | RW | GPIO97 DSP0 N1-priority interrupt. |
| 0 | DSP0N1GPIO96 | RW | GPIO96 DSP0 N1-priority interrupt. |
| Instance 0 Address: | 0x400103C0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO31
0x0 |
DSP1N0GPIO30
0x0 |
DSP1N0GPIO29
0x0 |
DSP1N0GPIO28
0x0 |
DSP1N0GPIO27
0x0 |
DSP1N0GPIO26
0x0 |
DSP1N0GPIO25
0x0 |
DSP1N0GPIO24
0x0 |
DSP1N0GPIO23
0x0 |
DSP1N0GPIO22
0x0 |
DSP1N0GPIO21
0x0 |
DSP1N0GPIO20
0x0 |
DSP1N0GPIO19
0x0 |
DSP1N0GPIO18
0x0 |
DSP1N0GPIO17
0x0 |
DSP1N0GPIO16
0x0 |
DSP1N0GPIO15
0x0 |
DSP1N0GPIO14
0x0 |
DSP1N0GPIO13
0x0 |
DSP1N0GPIO12
0x0 |
DSP1N0GPIO11
0x0 |
DSP1N0GPIO10
0x0 |
DSP1N0GPIO9
0x0 |
DSP1N0GPIO8
0x0 |
DSP1N0GPIO7
0x0 |
DSP1N0GPIO6
0x0 |
DSP1N0GPIO5
0x0 |
DSP1N0GPIO4
0x0 |
DSP1N0GPIO3
0x0 |
DSP1N0GPIO2
0x0 |
DSP1N0GPIO1
0x0 |
DSP1N0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO31 | RW | GPIO31 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO30 | RW | GPIO30 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO29 | RW | GPIO29 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO28 | RW | GPIO28 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO27 | RW | GPIO27 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO26 | RW | GPIO26 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO25 | RW | GPIO25 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO24 | RW | GPIO24 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO23 | RW | GPIO23 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO22 | RW | GPIO22 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO21 | RW | GPIO21 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO20 | RW | GPIO20 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO19 | RW | GPIO19 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO18 | RW | GPIO18 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO17 | RW | GPIO17 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO16 | RW | GPIO16 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO15 | RW | GPIO15 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO14 | RW | GPIO14 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO13 | RW | GPIO13 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO12 | RW | GPIO12 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO11 | RW | GPIO11 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO10 | RW | GPIO10 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO9 | RW | GPIO9 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO8 | RW | GPIO8 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO7 | RW | GPIO7 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO6 | RW | GPIO6 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO5 | RW | GPIO5 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO4 | RW | GPIO4 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO3 | RW | GPIO3 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO2 | RW | GPIO2 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO1 | RW | GPIO1 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO0 | RW | GPIO0 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103C4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO31
0x0 |
DSP1N0GPIO30
0x0 |
DSP1N0GPIO29
0x0 |
DSP1N0GPIO28
0x0 |
DSP1N0GPIO27
0x0 |
DSP1N0GPIO26
0x0 |
DSP1N0GPIO25
0x0 |
DSP1N0GPIO24
0x0 |
DSP1N0GPIO23
0x0 |
DSP1N0GPIO22
0x0 |
DSP1N0GPIO21
0x0 |
DSP1N0GPIO20
0x0 |
DSP1N0GPIO19
0x0 |
DSP1N0GPIO18
0x0 |
DSP1N0GPIO17
0x0 |
DSP1N0GPIO16
0x0 |
DSP1N0GPIO15
0x0 |
DSP1N0GPIO14
0x0 |
DSP1N0GPIO13
0x0 |
DSP1N0GPIO12
0x0 |
DSP1N0GPIO11
0x0 |
DSP1N0GPIO10
0x0 |
DSP1N0GPIO9
0x0 |
DSP1N0GPIO8
0x0 |
DSP1N0GPIO7
0x0 |
DSP1N0GPIO6
0x0 |
DSP1N0GPIO5
0x0 |
DSP1N0GPIO4
0x0 |
DSP1N0GPIO3
0x0 |
DSP1N0GPIO2
0x0 |
DSP1N0GPIO1
0x0 |
DSP1N0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO31 | RW | GPIO31 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO30 | RW | GPIO30 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO29 | RW | GPIO29 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO28 | RW | GPIO28 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO27 | RW | GPIO27 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO26 | RW | GPIO26 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO25 | RW | GPIO25 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO24 | RW | GPIO24 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO23 | RW | GPIO23 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO22 | RW | GPIO22 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO21 | RW | GPIO21 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO20 | RW | GPIO20 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO19 | RW | GPIO19 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO18 | RW | GPIO18 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO17 | RW | GPIO17 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO16 | RW | GPIO16 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO15 | RW | GPIO15 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO14 | RW | GPIO14 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO13 | RW | GPIO13 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO12 | RW | GPIO12 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO11 | RW | GPIO11 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO10 | RW | GPIO10 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO9 | RW | GPIO9 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO8 | RW | GPIO8 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO7 | RW | GPIO7 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO6 | RW | GPIO6 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO5 | RW | GPIO5 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO4 | RW | GPIO4 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO3 | RW | GPIO3 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO2 | RW | GPIO2 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO1 | RW | GPIO1 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO0 | RW | GPIO0 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103C8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO31
0x0 |
DSP1N0GPIO30
0x0 |
DSP1N0GPIO29
0x0 |
DSP1N0GPIO28
0x0 |
DSP1N0GPIO27
0x0 |
DSP1N0GPIO26
0x0 |
DSP1N0GPIO25
0x0 |
DSP1N0GPIO24
0x0 |
DSP1N0GPIO23
0x0 |
DSP1N0GPIO22
0x0 |
DSP1N0GPIO21
0x0 |
DSP1N0GPIO20
0x0 |
DSP1N0GPIO19
0x0 |
DSP1N0GPIO18
0x0 |
DSP1N0GPIO17
0x0 |
DSP1N0GPIO16
0x0 |
DSP1N0GPIO15
0x0 |
DSP1N0GPIO14
0x0 |
DSP1N0GPIO13
0x0 |
DSP1N0GPIO12
0x0 |
DSP1N0GPIO11
0x0 |
DSP1N0GPIO10
0x0 |
DSP1N0GPIO9
0x0 |
DSP1N0GPIO8
0x0 |
DSP1N0GPIO7
0x0 |
DSP1N0GPIO6
0x0 |
DSP1N0GPIO5
0x0 |
DSP1N0GPIO4
0x0 |
DSP1N0GPIO3
0x0 |
DSP1N0GPIO2
0x0 |
DSP1N0GPIO1
0x0 |
DSP1N0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO31 | RW | GPIO31 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO30 | RW | GPIO30 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO29 | RW | GPIO29 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO28 | RW | GPIO28 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO27 | RW | GPIO27 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO26 | RW | GPIO26 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO25 | RW | GPIO25 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO24 | RW | GPIO24 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO23 | RW | GPIO23 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO22 | RW | GPIO22 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO21 | RW | GPIO21 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO20 | RW | GPIO20 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO19 | RW | GPIO19 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO18 | RW | GPIO18 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO17 | RW | GPIO17 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO16 | RW | GPIO16 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO15 | RW | GPIO15 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO14 | RW | GPIO14 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO13 | RW | GPIO13 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO12 | RW | GPIO12 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO11 | RW | GPIO11 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO10 | RW | GPIO10 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO9 | RW | GPIO9 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO8 | RW | GPIO8 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO7 | RW | GPIO7 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO6 | RW | GPIO6 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO5 | RW | GPIO5 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO4 | RW | GPIO4 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO3 | RW | GPIO3 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO2 | RW | GPIO2 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO1 | RW | GPIO1 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO0 | RW | GPIO0 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103CC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO31
0x0 |
DSP1N0GPIO30
0x0 |
DSP1N0GPIO29
0x0 |
DSP1N0GPIO28
0x0 |
DSP1N0GPIO27
0x0 |
DSP1N0GPIO26
0x0 |
DSP1N0GPIO25
0x0 |
DSP1N0GPIO24
0x0 |
DSP1N0GPIO23
0x0 |
DSP1N0GPIO22
0x0 |
DSP1N0GPIO21
0x0 |
DSP1N0GPIO20
0x0 |
DSP1N0GPIO19
0x0 |
DSP1N0GPIO18
0x0 |
DSP1N0GPIO17
0x0 |
DSP1N0GPIO16
0x0 |
DSP1N0GPIO15
0x0 |
DSP1N0GPIO14
0x0 |
DSP1N0GPIO13
0x0 |
DSP1N0GPIO12
0x0 |
DSP1N0GPIO11
0x0 |
DSP1N0GPIO10
0x0 |
DSP1N0GPIO9
0x0 |
DSP1N0GPIO8
0x0 |
DSP1N0GPIO7
0x0 |
DSP1N0GPIO6
0x0 |
DSP1N0GPIO5
0x0 |
DSP1N0GPIO4
0x0 |
DSP1N0GPIO3
0x0 |
DSP1N0GPIO2
0x0 |
DSP1N0GPIO1
0x0 |
DSP1N0GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO31 | RW | GPIO31 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO30 | RW | GPIO30 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO29 | RW | GPIO29 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO28 | RW | GPIO28 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO27 | RW | GPIO27 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO26 | RW | GPIO26 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO25 | RW | GPIO25 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO24 | RW | GPIO24 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO23 | RW | GPIO23 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO22 | RW | GPIO22 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO21 | RW | GPIO21 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO20 | RW | GPIO20 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO19 | RW | GPIO19 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO18 | RW | GPIO18 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO17 | RW | GPIO17 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO16 | RW | GPIO16 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO15 | RW | GPIO15 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO14 | RW | GPIO14 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO13 | RW | GPIO13 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO12 | RW | GPIO12 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO11 | RW | GPIO11 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO10 | RW | GPIO10 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO9 | RW | GPIO9 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO8 | RW | GPIO8 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO7 | RW | GPIO7 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO6 | RW | GPIO6 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO5 | RW | GPIO5 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO4 | RW | GPIO4 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO3 | RW | GPIO3 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO2 | RW | GPIO2 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO1 | RW | GPIO1 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO0 | RW | GPIO0 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103D0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO63
0x0 |
DSP1N0GPIO62
0x0 |
DSP1N0GPIO61
0x0 |
DSP1N0GPIO60
0x0 |
DSP1N0GPIO59
0x0 |
DSP1N0GPIO58
0x0 |
DSP1N0GPIO57
0x0 |
DSP1N0GPIO56
0x0 |
DSP1N0GPIO55
0x0 |
DSP1N0GPIO54
0x0 |
DSP1N0GPIO53
0x0 |
DSP1N0GPIO52
0x0 |
DSP1N0GPIO51
0x0 |
DSP1N0GPIO50
0x0 |
DSP1N0GPIO49
0x0 |
DSP1N0GPIO48
0x0 |
DSP1N0GPIO47
0x0 |
DSP1N0GPIO46
0x0 |
DSP1N0GPIO45
0x0 |
DSP1N0GPIO44
0x0 |
DSP1N0GPIO43
0x0 |
DSP1N0GPIO42
0x0 |
DSP1N0GPIO41
0x0 |
DSP1N0GPIO40
0x0 |
DSP1N0GPIO39
0x0 |
DSP1N0GPIO38
0x0 |
DSP1N0GPIO37
0x0 |
DSP1N0GPIO36
0x0 |
DSP1N0GPIO35
0x0 |
DSP1N0GPIO34
0x0 |
DSP1N0GPIO33
0x0 |
DSP1N0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO63 | RW | GPIO63 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO62 | RW | GPIO62 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO61 | RW | GPIO61 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO60 | RW | GPIO60 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO59 | RW | GPIO59 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO58 | RW | GPIO58 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO57 | RW | GPIO57 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO56 | RW | GPIO56 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO55 | RW | GPIO55 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO54 | RW | GPIO54 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO53 | RW | GPIO53 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO52 | RW | GPIO52 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO51 | RW | GPIO51 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO50 | RW | GPIO50 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO49 | RW | GPIO49 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO48 | RW | GPIO48 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO47 | RW | GPIO47 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO46 | RW | GPIO46 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO45 | RW | GPIO45 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO44 | RW | GPIO44 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO43 | RW | GPIO43 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO42 | RW | GPIO42 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO41 | RW | GPIO41 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO40 | RW | GPIO40 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO39 | RW | GPIO39 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO38 | RW | GPIO38 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO37 | RW | GPIO37 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO36 | RW | GPIO36 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO35 | RW | GPIO35 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO34 | RW | GPIO34 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO33 | RW | GPIO33 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO32 | RW | GPIO32 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103D4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO63
0x0 |
DSP1N0GPIO62
0x0 |
DSP1N0GPIO61
0x0 |
DSP1N0GPIO60
0x0 |
DSP1N0GPIO59
0x0 |
DSP1N0GPIO58
0x0 |
DSP1N0GPIO57
0x0 |
DSP1N0GPIO56
0x0 |
DSP1N0GPIO55
0x0 |
DSP1N0GPIO54
0x0 |
DSP1N0GPIO53
0x0 |
DSP1N0GPIO52
0x0 |
DSP1N0GPIO51
0x0 |
DSP1N0GPIO50
0x0 |
DSP1N0GPIO49
0x0 |
DSP1N0GPIO48
0x0 |
DSP1N0GPIO47
0x0 |
DSP1N0GPIO46
0x0 |
DSP1N0GPIO45
0x0 |
DSP1N0GPIO44
0x0 |
DSP1N0GPIO43
0x0 |
DSP1N0GPIO42
0x0 |
DSP1N0GPIO41
0x0 |
DSP1N0GPIO40
0x0 |
DSP1N0GPIO39
0x0 |
DSP1N0GPIO38
0x0 |
DSP1N0GPIO37
0x0 |
DSP1N0GPIO36
0x0 |
DSP1N0GPIO35
0x0 |
DSP1N0GPIO34
0x0 |
DSP1N0GPIO33
0x0 |
DSP1N0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO63 | RW | GPIO63 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO62 | RW | GPIO62 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO61 | RW | GPIO61 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO60 | RW | GPIO60 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO59 | RW | GPIO59 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO58 | RW | GPIO58 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO57 | RW | GPIO57 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO56 | RW | GPIO56 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO55 | RW | GPIO55 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO54 | RW | GPIO54 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO53 | RW | GPIO53 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO52 | RW | GPIO52 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO51 | RW | GPIO51 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO50 | RW | GPIO50 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO49 | RW | GPIO49 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO48 | RW | GPIO48 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO47 | RW | GPIO47 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO46 | RW | GPIO46 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO45 | RW | GPIO45 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO44 | RW | GPIO44 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO43 | RW | GPIO43 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO42 | RW | GPIO42 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO41 | RW | GPIO41 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO40 | RW | GPIO40 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO39 | RW | GPIO39 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO38 | RW | GPIO38 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO37 | RW | GPIO37 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO36 | RW | GPIO36 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO35 | RW | GPIO35 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO34 | RW | GPIO34 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO33 | RW | GPIO33 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO32 | RW | GPIO32 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103D8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO63
0x0 |
DSP1N0GPIO62
0x0 |
DSP1N0GPIO61
0x0 |
DSP1N0GPIO60
0x0 |
DSP1N0GPIO59
0x0 |
DSP1N0GPIO58
0x0 |
DSP1N0GPIO57
0x0 |
DSP1N0GPIO56
0x0 |
DSP1N0GPIO55
0x0 |
DSP1N0GPIO54
0x0 |
DSP1N0GPIO53
0x0 |
DSP1N0GPIO52
0x0 |
DSP1N0GPIO51
0x0 |
DSP1N0GPIO50
0x0 |
DSP1N0GPIO49
0x0 |
DSP1N0GPIO48
0x0 |
DSP1N0GPIO47
0x0 |
DSP1N0GPIO46
0x0 |
DSP1N0GPIO45
0x0 |
DSP1N0GPIO44
0x0 |
DSP1N0GPIO43
0x0 |
DSP1N0GPIO42
0x0 |
DSP1N0GPIO41
0x0 |
DSP1N0GPIO40
0x0 |
DSP1N0GPIO39
0x0 |
DSP1N0GPIO38
0x0 |
DSP1N0GPIO37
0x0 |
DSP1N0GPIO36
0x0 |
DSP1N0GPIO35
0x0 |
DSP1N0GPIO34
0x0 |
DSP1N0GPIO33
0x0 |
DSP1N0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO63 | RW | GPIO63 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO62 | RW | GPIO62 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO61 | RW | GPIO61 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO60 | RW | GPIO60 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO59 | RW | GPIO59 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO58 | RW | GPIO58 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO57 | RW | GPIO57 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO56 | RW | GPIO56 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO55 | RW | GPIO55 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO54 | RW | GPIO54 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO53 | RW | GPIO53 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO52 | RW | GPIO52 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO51 | RW | GPIO51 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO50 | RW | GPIO50 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO49 | RW | GPIO49 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO48 | RW | GPIO48 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO47 | RW | GPIO47 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO46 | RW | GPIO46 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO45 | RW | GPIO45 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO44 | RW | GPIO44 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO43 | RW | GPIO43 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO42 | RW | GPIO42 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO41 | RW | GPIO41 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO40 | RW | GPIO40 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO39 | RW | GPIO39 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO38 | RW | GPIO38 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO37 | RW | GPIO37 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO36 | RW | GPIO36 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO35 | RW | GPIO35 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO34 | RW | GPIO34 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO33 | RW | GPIO33 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO32 | RW | GPIO32 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103DC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO63
0x0 |
DSP1N0GPIO62
0x0 |
DSP1N0GPIO61
0x0 |
DSP1N0GPIO60
0x0 |
DSP1N0GPIO59
0x0 |
DSP1N0GPIO58
0x0 |
DSP1N0GPIO57
0x0 |
DSP1N0GPIO56
0x0 |
DSP1N0GPIO55
0x0 |
DSP1N0GPIO54
0x0 |
DSP1N0GPIO53
0x0 |
DSP1N0GPIO52
0x0 |
DSP1N0GPIO51
0x0 |
DSP1N0GPIO50
0x0 |
DSP1N0GPIO49
0x0 |
DSP1N0GPIO48
0x0 |
DSP1N0GPIO47
0x0 |
DSP1N0GPIO46
0x0 |
DSP1N0GPIO45
0x0 |
DSP1N0GPIO44
0x0 |
DSP1N0GPIO43
0x0 |
DSP1N0GPIO42
0x0 |
DSP1N0GPIO41
0x0 |
DSP1N0GPIO40
0x0 |
DSP1N0GPIO39
0x0 |
DSP1N0GPIO38
0x0 |
DSP1N0GPIO37
0x0 |
DSP1N0GPIO36
0x0 |
DSP1N0GPIO35
0x0 |
DSP1N0GPIO34
0x0 |
DSP1N0GPIO33
0x0 |
DSP1N0GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO63 | RW | GPIO63 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO62 | RW | GPIO62 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO61 | RW | GPIO61 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO60 | RW | GPIO60 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO59 | RW | GPIO59 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO58 | RW | GPIO58 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO57 | RW | GPIO57 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO56 | RW | GPIO56 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO55 | RW | GPIO55 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO54 | RW | GPIO54 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO53 | RW | GPIO53 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO52 | RW | GPIO52 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO51 | RW | GPIO51 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO50 | RW | GPIO50 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO49 | RW | GPIO49 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO48 | RW | GPIO48 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO47 | RW | GPIO47 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO46 | RW | GPIO46 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO45 | RW | GPIO45 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO44 | RW | GPIO44 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO43 | RW | GPIO43 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO42 | RW | GPIO42 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO41 | RW | GPIO41 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO40 | RW | GPIO40 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO39 | RW | GPIO39 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO38 | RW | GPIO38 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO37 | RW | GPIO37 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO36 | RW | GPIO36 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO35 | RW | GPIO35 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO34 | RW | GPIO34 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO33 | RW | GPIO33 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO32 | RW | GPIO32 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103E0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO95
0x0 |
DSP1N0GPIO94
0x0 |
DSP1N0GPIO93
0x0 |
DSP1N0GPIO92
0x0 |
DSP1N0GPIO91
0x0 |
DSP1N0GPIO90
0x0 |
DSP1N0GPIO89
0x0 |
DSP1N0GPIO88
0x0 |
DSP1N0GPIO87
0x0 |
DSP1N0GPIO86
0x0 |
DSP1N0GPIO85
0x0 |
DSP1N0GPIO84
0x0 |
DSP1N0GPIO83
0x0 |
DSP1N0GPIO82
0x0 |
DSP1N0GPIO81
0x0 |
DSP1N0GPIO80
0x0 |
DSP1N0GPIO79
0x0 |
DSP1N0GPIO78
0x0 |
DSP1N0GPIO77
0x0 |
DSP1N0GPIO76
0x0 |
DSP1N0GPIO75
0x0 |
DSP1N0GPIO74
0x0 |
DSP1N0GPIO73
0x0 |
DSP1N0GPIO72
0x0 |
DSP1N0GPIO71
0x0 |
DSP1N0GPIO70
0x0 |
DSP1N0GPIO69
0x0 |
DSP1N0GPIO68
0x0 |
DSP1N0GPIO67
0x0 |
DSP1N0GPIO66
0x0 |
DSP1N0GPIO65
0x0 |
DSP1N0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO95 | RW | GPIO95 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO94 | RW | GPIO94 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO93 | RW | GPIO93 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO92 | RW | GPIO92 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO91 | RW | GPIO91 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO90 | RW | GPIO90 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO89 | RW | GPIO89 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO88 | RW | GPIO88 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO87 | RW | GPIO87 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO86 | RW | GPIO86 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO85 | RW | GPIO85 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO84 | RW | GPIO84 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO83 | RW | GPIO83 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO82 | RW | GPIO82 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO81 | RW | GPIO81 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO80 | RW | GPIO80 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO79 | RW | GPIO79 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO78 | RW | GPIO78 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO77 | RW | GPIO77 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO76 | RW | GPIO76 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO75 | RW | GPIO75 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO74 | RW | GPIO74 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO73 | RW | GPIO73 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO72 | RW | GPIO72 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO71 | RW | GPIO71 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO70 | RW | GPIO70 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO69 | RW | GPIO69 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO68 | RW | GPIO68 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO67 | RW | GPIO67 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO66 | RW | GPIO66 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO65 | RW | GPIO65 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO64 | RW | GPIO64 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103E4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO95
0x0 |
DSP1N0GPIO94
0x0 |
DSP1N0GPIO93
0x0 |
DSP1N0GPIO92
0x0 |
DSP1N0GPIO91
0x0 |
DSP1N0GPIO90
0x0 |
DSP1N0GPIO89
0x0 |
DSP1N0GPIO88
0x0 |
DSP1N0GPIO87
0x0 |
DSP1N0GPIO86
0x0 |
DSP1N0GPIO85
0x0 |
DSP1N0GPIO84
0x0 |
DSP1N0GPIO83
0x0 |
DSP1N0GPIO82
0x0 |
DSP1N0GPIO81
0x0 |
DSP1N0GPIO80
0x0 |
DSP1N0GPIO79
0x0 |
DSP1N0GPIO78
0x0 |
DSP1N0GPIO77
0x0 |
DSP1N0GPIO76
0x0 |
DSP1N0GPIO75
0x0 |
DSP1N0GPIO74
0x0 |
DSP1N0GPIO73
0x0 |
DSP1N0GPIO72
0x0 |
DSP1N0GPIO71
0x0 |
DSP1N0GPIO70
0x0 |
DSP1N0GPIO69
0x0 |
DSP1N0GPIO68
0x0 |
DSP1N0GPIO67
0x0 |
DSP1N0GPIO66
0x0 |
DSP1N0GPIO65
0x0 |
DSP1N0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO95 | RW | GPIO95 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO94 | RW | GPIO94 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO93 | RW | GPIO93 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO92 | RW | GPIO92 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO91 | RW | GPIO91 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO90 | RW | GPIO90 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO89 | RW | GPIO89 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO88 | RW | GPIO88 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO87 | RW | GPIO87 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO86 | RW | GPIO86 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO85 | RW | GPIO85 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO84 | RW | GPIO84 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO83 | RW | GPIO83 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO82 | RW | GPIO82 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO81 | RW | GPIO81 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO80 | RW | GPIO80 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO79 | RW | GPIO79 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO78 | RW | GPIO78 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO77 | RW | GPIO77 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO76 | RW | GPIO76 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO75 | RW | GPIO75 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO74 | RW | GPIO74 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO73 | RW | GPIO73 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO72 | RW | GPIO72 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO71 | RW | GPIO71 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO70 | RW | GPIO70 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO69 | RW | GPIO69 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO68 | RW | GPIO68 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO67 | RW | GPIO67 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO66 | RW | GPIO66 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO65 | RW | GPIO65 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO64 | RW | GPIO64 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103E8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO95
0x0 |
DSP1N0GPIO94
0x0 |
DSP1N0GPIO93
0x0 |
DSP1N0GPIO92
0x0 |
DSP1N0GPIO91
0x0 |
DSP1N0GPIO90
0x0 |
DSP1N0GPIO89
0x0 |
DSP1N0GPIO88
0x0 |
DSP1N0GPIO87
0x0 |
DSP1N0GPIO86
0x0 |
DSP1N0GPIO85
0x0 |
DSP1N0GPIO84
0x0 |
DSP1N0GPIO83
0x0 |
DSP1N0GPIO82
0x0 |
DSP1N0GPIO81
0x0 |
DSP1N0GPIO80
0x0 |
DSP1N0GPIO79
0x0 |
DSP1N0GPIO78
0x0 |
DSP1N0GPIO77
0x0 |
DSP1N0GPIO76
0x0 |
DSP1N0GPIO75
0x0 |
DSP1N0GPIO74
0x0 |
DSP1N0GPIO73
0x0 |
DSP1N0GPIO72
0x0 |
DSP1N0GPIO71
0x0 |
DSP1N0GPIO70
0x0 |
DSP1N0GPIO69
0x0 |
DSP1N0GPIO68
0x0 |
DSP1N0GPIO67
0x0 |
DSP1N0GPIO66
0x0 |
DSP1N0GPIO65
0x0 |
DSP1N0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO95 | RW | GPIO95 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO94 | RW | GPIO94 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO93 | RW | GPIO93 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO92 | RW | GPIO92 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO91 | RW | GPIO91 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO90 | RW | GPIO90 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO89 | RW | GPIO89 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO88 | RW | GPIO88 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO87 | RW | GPIO87 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO86 | RW | GPIO86 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO85 | RW | GPIO85 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO84 | RW | GPIO84 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO83 | RW | GPIO83 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO82 | RW | GPIO82 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO81 | RW | GPIO81 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO80 | RW | GPIO80 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO79 | RW | GPIO79 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO78 | RW | GPIO78 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO77 | RW | GPIO77 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO76 | RW | GPIO76 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO75 | RW | GPIO75 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO74 | RW | GPIO74 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO73 | RW | GPIO73 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO72 | RW | GPIO72 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO71 | RW | GPIO71 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO70 | RW | GPIO70 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO69 | RW | GPIO69 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO68 | RW | GPIO68 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO67 | RW | GPIO67 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO66 | RW | GPIO66 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO65 | RW | GPIO65 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO64 | RW | GPIO64 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103EC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO95
0x0 |
DSP1N0GPIO94
0x0 |
DSP1N0GPIO93
0x0 |
DSP1N0GPIO92
0x0 |
DSP1N0GPIO91
0x0 |
DSP1N0GPIO90
0x0 |
DSP1N0GPIO89
0x0 |
DSP1N0GPIO88
0x0 |
DSP1N0GPIO87
0x0 |
DSP1N0GPIO86
0x0 |
DSP1N0GPIO85
0x0 |
DSP1N0GPIO84
0x0 |
DSP1N0GPIO83
0x0 |
DSP1N0GPIO82
0x0 |
DSP1N0GPIO81
0x0 |
DSP1N0GPIO80
0x0 |
DSP1N0GPIO79
0x0 |
DSP1N0GPIO78
0x0 |
DSP1N0GPIO77
0x0 |
DSP1N0GPIO76
0x0 |
DSP1N0GPIO75
0x0 |
DSP1N0GPIO74
0x0 |
DSP1N0GPIO73
0x0 |
DSP1N0GPIO72
0x0 |
DSP1N0GPIO71
0x0 |
DSP1N0GPIO70
0x0 |
DSP1N0GPIO69
0x0 |
DSP1N0GPIO68
0x0 |
DSP1N0GPIO67
0x0 |
DSP1N0GPIO66
0x0 |
DSP1N0GPIO65
0x0 |
DSP1N0GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO95 | RW | GPIO95 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO94 | RW | GPIO94 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO93 | RW | GPIO93 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO92 | RW | GPIO92 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO91 | RW | GPIO91 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO90 | RW | GPIO90 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO89 | RW | GPIO89 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO88 | RW | GPIO88 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO87 | RW | GPIO87 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO86 | RW | GPIO86 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO85 | RW | GPIO85 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO84 | RW | GPIO84 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO83 | RW | GPIO83 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO82 | RW | GPIO82 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO81 | RW | GPIO81 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO80 | RW | GPIO80 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO79 | RW | GPIO79 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO78 | RW | GPIO78 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO77 | RW | GPIO77 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO76 | RW | GPIO76 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO75 | RW | GPIO75 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO74 | RW | GPIO74 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO73 | RW | GPIO73 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO72 | RW | GPIO72 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO71 | RW | GPIO71 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO70 | RW | GPIO70 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO69 | RW | GPIO69 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO68 | RW | GPIO68 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO67 | RW | GPIO67 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO66 | RW | GPIO66 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO65 | RW | GPIO65 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO64 | RW | GPIO64 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103F0 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO127
0x0 |
DSP1N0GPIO126
0x0 |
DSP1N0GPIO125
0x0 |
DSP1N0GPIO124
0x0 |
DSP1N0GPIO123
0x0 |
DSP1N0GPIO122
0x0 |
DSP1N0GPIO121
0x0 |
DSP1N0GPIO120
0x0 |
DSP1N0GPIO119
0x0 |
DSP1N0GPIO118
0x0 |
DSP1N0GPIO117
0x0 |
DSP1N0GPIO116
0x0 |
DSP1N0GPIO115
0x0 |
DSP1N0GPIO114
0x0 |
DSP1N0GPIO113
0x0 |
DSP1N0GPIO112
0x0 |
DSP1N0GPIO111
0x0 |
DSP1N0GPIO110
0x0 |
DSP1N0GPIO109
0x0 |
DSP1N0GPIO108
0x0 |
DSP1N0GPIO107
0x0 |
DSP1N0GPIO106
0x0 |
DSP1N0GPIO105
0x0 |
DSP1N0GPIO104
0x0 |
DSP1N0GPIO103
0x0 |
DSP1N0GPIO102
0x0 |
DSP1N0GPIO101
0x0 |
DSP1N0GPIO100
0x0 |
DSP1N0GPIO99
0x0 |
DSP1N0GPIO98
0x0 |
DSP1N0GPIO97
0x0 |
DSP1N0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO127 | RW | GPIO127 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO126 | RW | GPIO126 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO125 | RW | GPIO125 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO124 | RW | GPIO124 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO123 | RW | GPIO123 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO122 | RW | GPIO122 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO121 | RW | GPIO121 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO120 | RW | GPIO120 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO119 | RW | GPIO119 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO118 | RW | GPIO118 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO117 | RW | GPIO117 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO116 | RW | GPIO116 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO115 | RW | GPIO115 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO114 | RW | GPIO114 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO113 | RW | GPIO113 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO112 | RW | GPIO112 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO111 | RW | GPIO111 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO110 | RW | GPIO110 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO109 | RW | GPIO109 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO108 | RW | GPIO108 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO107 | RW | GPIO107 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO106 | RW | GPIO106 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO105 | RW | GPIO105 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO104 | RW | GPIO104 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO103 | RW | GPIO103 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO102 | RW | GPIO102 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO101 | RW | GPIO101 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO100 | RW | GPIO100 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO99 | RW | GPIO99 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO98 | RW | GPIO98 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO97 | RW | GPIO97 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO96 | RW | GPIO96 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103F4 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO127
0x0 |
DSP1N0GPIO126
0x0 |
DSP1N0GPIO125
0x0 |
DSP1N0GPIO124
0x0 |
DSP1N0GPIO123
0x0 |
DSP1N0GPIO122
0x0 |
DSP1N0GPIO121
0x0 |
DSP1N0GPIO120
0x0 |
DSP1N0GPIO119
0x0 |
DSP1N0GPIO118
0x0 |
DSP1N0GPIO117
0x0 |
DSP1N0GPIO116
0x0 |
DSP1N0GPIO115
0x0 |
DSP1N0GPIO114
0x0 |
DSP1N0GPIO113
0x0 |
DSP1N0GPIO112
0x0 |
DSP1N0GPIO111
0x0 |
DSP1N0GPIO110
0x0 |
DSP1N0GPIO109
0x0 |
DSP1N0GPIO108
0x0 |
DSP1N0GPIO107
0x0 |
DSP1N0GPIO106
0x0 |
DSP1N0GPIO105
0x0 |
DSP1N0GPIO104
0x0 |
DSP1N0GPIO103
0x0 |
DSP1N0GPIO102
0x0 |
DSP1N0GPIO101
0x0 |
DSP1N0GPIO100
0x0 |
DSP1N0GPIO99
0x0 |
DSP1N0GPIO98
0x0 |
DSP1N0GPIO97
0x0 |
DSP1N0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO127 | RW | GPIO127 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO126 | RW | GPIO126 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO125 | RW | GPIO125 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO124 | RW | GPIO124 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO123 | RW | GPIO123 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO122 | RW | GPIO122 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO121 | RW | GPIO121 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO120 | RW | GPIO120 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO119 | RW | GPIO119 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO118 | RW | GPIO118 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO117 | RW | GPIO117 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO116 | RW | GPIO116 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO115 | RW | GPIO115 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO114 | RW | GPIO114 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO113 | RW | GPIO113 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO112 | RW | GPIO112 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO111 | RW | GPIO111 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO110 | RW | GPIO110 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO109 | RW | GPIO109 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO108 | RW | GPIO108 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO107 | RW | GPIO107 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO106 | RW | GPIO106 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO105 | RW | GPIO105 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO104 | RW | GPIO104 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO103 | RW | GPIO103 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO102 | RW | GPIO102 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO101 | RW | GPIO101 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO100 | RW | GPIO100 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO99 | RW | GPIO99 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO98 | RW | GPIO98 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO97 | RW | GPIO97 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO96 | RW | GPIO96 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103F8 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO127
0x0 |
DSP1N0GPIO126
0x0 |
DSP1N0GPIO125
0x0 |
DSP1N0GPIO124
0x0 |
DSP1N0GPIO123
0x0 |
DSP1N0GPIO122
0x0 |
DSP1N0GPIO121
0x0 |
DSP1N0GPIO120
0x0 |
DSP1N0GPIO119
0x0 |
DSP1N0GPIO118
0x0 |
DSP1N0GPIO117
0x0 |
DSP1N0GPIO116
0x0 |
DSP1N0GPIO115
0x0 |
DSP1N0GPIO114
0x0 |
DSP1N0GPIO113
0x0 |
DSP1N0GPIO112
0x0 |
DSP1N0GPIO111
0x0 |
DSP1N0GPIO110
0x0 |
DSP1N0GPIO109
0x0 |
DSP1N0GPIO108
0x0 |
DSP1N0GPIO107
0x0 |
DSP1N0GPIO106
0x0 |
DSP1N0GPIO105
0x0 |
DSP1N0GPIO104
0x0 |
DSP1N0GPIO103
0x0 |
DSP1N0GPIO102
0x0 |
DSP1N0GPIO101
0x0 |
DSP1N0GPIO100
0x0 |
DSP1N0GPIO99
0x0 |
DSP1N0GPIO98
0x0 |
DSP1N0GPIO97
0x0 |
DSP1N0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO127 | RW | GPIO127 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO126 | RW | GPIO126 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO125 | RW | GPIO125 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO124 | RW | GPIO124 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO123 | RW | GPIO123 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO122 | RW | GPIO122 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO121 | RW | GPIO121 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO120 | RW | GPIO120 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO119 | RW | GPIO119 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO118 | RW | GPIO118 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO117 | RW | GPIO117 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO116 | RW | GPIO116 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO115 | RW | GPIO115 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO114 | RW | GPIO114 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO113 | RW | GPIO113 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO112 | RW | GPIO112 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO111 | RW | GPIO111 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO110 | RW | GPIO110 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO109 | RW | GPIO109 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO108 | RW | GPIO108 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO107 | RW | GPIO107 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO106 | RW | GPIO106 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO105 | RW | GPIO105 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO104 | RW | GPIO104 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO103 | RW | GPIO103 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO102 | RW | GPIO102 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO101 | RW | GPIO101 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO100 | RW | GPIO100 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO99 | RW | GPIO99 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO98 | RW | GPIO98 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO97 | RW | GPIO97 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO96 | RW | GPIO96 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x400103FC |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N0GPIO127
0x0 |
DSP1N0GPIO126
0x0 |
DSP1N0GPIO125
0x0 |
DSP1N0GPIO124
0x0 |
DSP1N0GPIO123
0x0 |
DSP1N0GPIO122
0x0 |
DSP1N0GPIO121
0x0 |
DSP1N0GPIO120
0x0 |
DSP1N0GPIO119
0x0 |
DSP1N0GPIO118
0x0 |
DSP1N0GPIO117
0x0 |
DSP1N0GPIO116
0x0 |
DSP1N0GPIO115
0x0 |
DSP1N0GPIO114
0x0 |
DSP1N0GPIO113
0x0 |
DSP1N0GPIO112
0x0 |
DSP1N0GPIO111
0x0 |
DSP1N0GPIO110
0x0 |
DSP1N0GPIO109
0x0 |
DSP1N0GPIO108
0x0 |
DSP1N0GPIO107
0x0 |
DSP1N0GPIO106
0x0 |
DSP1N0GPIO105
0x0 |
DSP1N0GPIO104
0x0 |
DSP1N0GPIO103
0x0 |
DSP1N0GPIO102
0x0 |
DSP1N0GPIO101
0x0 |
DSP1N0GPIO100
0x0 |
DSP1N0GPIO99
0x0 |
DSP1N0GPIO98
0x0 |
DSP1N0GPIO97
0x0 |
DSP1N0GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N0GPIO127 | RW | GPIO127 DSP1 N0-priority interrupt. |
| 30 | DSP1N0GPIO126 | RW | GPIO126 DSP1 N0-priority interrupt. |
| 29 | DSP1N0GPIO125 | RW | GPIO125 DSP1 N0-priority interrupt. |
| 28 | DSP1N0GPIO124 | RW | GPIO124 DSP1 N0-priority interrupt. |
| 27 | DSP1N0GPIO123 | RW | GPIO123 DSP1 N0-priority interrupt. |
| 26 | DSP1N0GPIO122 | RW | GPIO122 DSP1 N0-priority interrupt. |
| 25 | DSP1N0GPIO121 | RW | GPIO121 DSP1 N0-priority interrupt. |
| 24 | DSP1N0GPIO120 | RW | GPIO120 DSP1 N0-priority interrupt. |
| 23 | DSP1N0GPIO119 | RW | GPIO119 DSP1 N0-priority interrupt. |
| 22 | DSP1N0GPIO118 | RW | GPIO118 DSP1 N0-priority interrupt. |
| 21 | DSP1N0GPIO117 | RW | GPIO117 DSP1 N0-priority interrupt. |
| 20 | DSP1N0GPIO116 | RW | GPIO116 DSP1 N0-priority interrupt. |
| 19 | DSP1N0GPIO115 | RW | GPIO115 DSP1 N0-priority interrupt. |
| 18 | DSP1N0GPIO114 | RW | GPIO114 DSP1 N0-priority interrupt. |
| 17 | DSP1N0GPIO113 | RW | GPIO113 DSP1 N0-priority interrupt. |
| 16 | DSP1N0GPIO112 | RW | GPIO112 DSP1 N0-priority interrupt. |
| 15 | DSP1N0GPIO111 | RW | GPIO111 DSP1 N0-priority interrupt. |
| 14 | DSP1N0GPIO110 | RW | GPIO110 DSP1 N0-priority interrupt. |
| 13 | DSP1N0GPIO109 | RW | GPIO109 DSP1 N0-priority interrupt. |
| 12 | DSP1N0GPIO108 | RW | GPIO108 DSP1 N0-priority interrupt. |
| 11 | DSP1N0GPIO107 | RW | GPIO107 DSP1 N0-priority interrupt. |
| 10 | DSP1N0GPIO106 | RW | GPIO106 DSP1 N0-priority interrupt. |
| 9 | DSP1N0GPIO105 | RW | GPIO105 DSP1 N0-priority interrupt. |
| 8 | DSP1N0GPIO104 | RW | GPIO104 DSP1 N0-priority interrupt. |
| 7 | DSP1N0GPIO103 | RW | GPIO103 DSP1 N0-priority interrupt. |
| 6 | DSP1N0GPIO102 | RW | GPIO102 DSP1 N0-priority interrupt. |
| 5 | DSP1N0GPIO101 | RW | GPIO101 DSP1 N0-priority interrupt. |
| 4 | DSP1N0GPIO100 | RW | GPIO100 DSP1 N0-priority interrupt. |
| 3 | DSP1N0GPIO99 | RW | GPIO99 DSP1 N0-priority interrupt. |
| 2 | DSP1N0GPIO98 | RW | GPIO98 DSP1 N0-priority interrupt. |
| 1 | DSP1N0GPIO97 | RW | GPIO97 DSP1 N0-priority interrupt. |
| 0 | DSP1N0GPIO96 | RW | GPIO96 DSP1 N0-priority interrupt. |
| Instance 0 Address: | 0x40010400 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO31
0x0 |
DSP1N1GPIO30
0x0 |
DSP1N1GPIO29
0x0 |
DSP1N1GPIO28
0x0 |
DSP1N1GPIO27
0x0 |
DSP1N1GPIO26
0x0 |
DSP1N1GPIO25
0x0 |
DSP1N1GPIO24
0x0 |
DSP1N1GPIO23
0x0 |
DSP1N1GPIO22
0x0 |
DSP1N1GPIO21
0x0 |
DSP1N1GPIO20
0x0 |
DSP1N1GPIO19
0x0 |
DSP1N1GPIO18
0x0 |
DSP1N1GPIO17
0x0 |
DSP1N1GPIO16
0x0 |
DSP1N1GPIO15
0x0 |
DSP1N1GPIO14
0x0 |
DSP1N1GPIO13
0x0 |
DSP1N1GPIO12
0x0 |
DSP1N1GPIO11
0x0 |
DSP1N1GPIO10
0x0 |
DSP1N1GPIO9
0x0 |
DSP1N1GPIO8
0x0 |
DSP1N1GPIO7
0x0 |
DSP1N1GPIO6
0x0 |
DSP1N1GPIO5
0x0 |
DSP1N1GPIO4
0x0 |
DSP1N1GPIO3
0x0 |
DSP1N1GPIO2
0x0 |
DSP1N1GPIO1
0x0 |
DSP1N1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO31 | RW | GPIO31 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO30 | RW | GPIO30 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO29 | RW | GPIO29 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO28 | RW | GPIO28 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO27 | RW | GPIO27 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO26 | RW | GPIO26 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO25 | RW | GPIO25 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO24 | RW | GPIO24 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO23 | RW | GPIO23 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO22 | RW | GPIO22 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO21 | RW | GPIO21 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO20 | RW | GPIO20 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO19 | RW | GPIO19 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO18 | RW | GPIO18 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO17 | RW | GPIO17 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO16 | RW | GPIO16 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO15 | RW | GPIO15 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO14 | RW | GPIO14 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO13 | RW | GPIO13 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO12 | RW | GPIO12 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO11 | RW | GPIO11 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO10 | RW | GPIO10 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO9 | RW | GPIO9 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO8 | RW | GPIO8 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO7 | RW | GPIO7 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO6 | RW | GPIO6 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO5 | RW | GPIO5 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO4 | RW | GPIO4 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO3 | RW | GPIO3 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO2 | RW | GPIO2 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO1 | RW | GPIO1 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO0 | RW | GPIO0 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010404 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO31
0x0 |
DSP1N1GPIO30
0x0 |
DSP1N1GPIO29
0x0 |
DSP1N1GPIO28
0x0 |
DSP1N1GPIO27
0x0 |
DSP1N1GPIO26
0x0 |
DSP1N1GPIO25
0x0 |
DSP1N1GPIO24
0x0 |
DSP1N1GPIO23
0x0 |
DSP1N1GPIO22
0x0 |
DSP1N1GPIO21
0x0 |
DSP1N1GPIO20
0x0 |
DSP1N1GPIO19
0x0 |
DSP1N1GPIO18
0x0 |
DSP1N1GPIO17
0x0 |
DSP1N1GPIO16
0x0 |
DSP1N1GPIO15
0x0 |
DSP1N1GPIO14
0x0 |
DSP1N1GPIO13
0x0 |
DSP1N1GPIO12
0x0 |
DSP1N1GPIO11
0x0 |
DSP1N1GPIO10
0x0 |
DSP1N1GPIO9
0x0 |
DSP1N1GPIO8
0x0 |
DSP1N1GPIO7
0x0 |
DSP1N1GPIO6
0x0 |
DSP1N1GPIO5
0x0 |
DSP1N1GPIO4
0x0 |
DSP1N1GPIO3
0x0 |
DSP1N1GPIO2
0x0 |
DSP1N1GPIO1
0x0 |
DSP1N1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO31 | RW | GPIO31 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO30 | RW | GPIO30 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO29 | RW | GPIO29 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO28 | RW | GPIO28 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO27 | RW | GPIO27 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO26 | RW | GPIO26 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO25 | RW | GPIO25 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO24 | RW | GPIO24 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO23 | RW | GPIO23 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO22 | RW | GPIO22 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO21 | RW | GPIO21 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO20 | RW | GPIO20 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO19 | RW | GPIO19 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO18 | RW | GPIO18 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO17 | RW | GPIO17 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO16 | RW | GPIO16 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO15 | RW | GPIO15 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO14 | RW | GPIO14 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO13 | RW | GPIO13 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO12 | RW | GPIO12 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO11 | RW | GPIO11 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO10 | RW | GPIO10 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO9 | RW | GPIO9 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO8 | RW | GPIO8 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO7 | RW | GPIO7 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO6 | RW | GPIO6 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO5 | RW | GPIO5 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO4 | RW | GPIO4 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO3 | RW | GPIO3 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO2 | RW | GPIO2 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO1 | RW | GPIO1 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO0 | RW | GPIO0 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010408 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO31
0x0 |
DSP1N1GPIO30
0x0 |
DSP1N1GPIO29
0x0 |
DSP1N1GPIO28
0x0 |
DSP1N1GPIO27
0x0 |
DSP1N1GPIO26
0x0 |
DSP1N1GPIO25
0x0 |
DSP1N1GPIO24
0x0 |
DSP1N1GPIO23
0x0 |
DSP1N1GPIO22
0x0 |
DSP1N1GPIO21
0x0 |
DSP1N1GPIO20
0x0 |
DSP1N1GPIO19
0x0 |
DSP1N1GPIO18
0x0 |
DSP1N1GPIO17
0x0 |
DSP1N1GPIO16
0x0 |
DSP1N1GPIO15
0x0 |
DSP1N1GPIO14
0x0 |
DSP1N1GPIO13
0x0 |
DSP1N1GPIO12
0x0 |
DSP1N1GPIO11
0x0 |
DSP1N1GPIO10
0x0 |
DSP1N1GPIO9
0x0 |
DSP1N1GPIO8
0x0 |
DSP1N1GPIO7
0x0 |
DSP1N1GPIO6
0x0 |
DSP1N1GPIO5
0x0 |
DSP1N1GPIO4
0x0 |
DSP1N1GPIO3
0x0 |
DSP1N1GPIO2
0x0 |
DSP1N1GPIO1
0x0 |
DSP1N1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO31 | RW | GPIO31 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO30 | RW | GPIO30 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO29 | RW | GPIO29 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO28 | RW | GPIO28 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO27 | RW | GPIO27 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO26 | RW | GPIO26 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO25 | RW | GPIO25 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO24 | RW | GPIO24 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO23 | RW | GPIO23 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO22 | RW | GPIO22 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO21 | RW | GPIO21 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO20 | RW | GPIO20 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO19 | RW | GPIO19 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO18 | RW | GPIO18 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO17 | RW | GPIO17 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO16 | RW | GPIO16 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO15 | RW | GPIO15 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO14 | RW | GPIO14 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO13 | RW | GPIO13 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO12 | RW | GPIO12 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO11 | RW | GPIO11 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO10 | RW | GPIO10 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO9 | RW | GPIO9 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO8 | RW | GPIO8 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO7 | RW | GPIO7 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO6 | RW | GPIO6 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO5 | RW | GPIO5 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO4 | RW | GPIO4 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO3 | RW | GPIO3 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO2 | RW | GPIO2 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO1 | RW | GPIO1 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO0 | RW | GPIO0 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x4001040C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO31
0x0 |
DSP1N1GPIO30
0x0 |
DSP1N1GPIO29
0x0 |
DSP1N1GPIO28
0x0 |
DSP1N1GPIO27
0x0 |
DSP1N1GPIO26
0x0 |
DSP1N1GPIO25
0x0 |
DSP1N1GPIO24
0x0 |
DSP1N1GPIO23
0x0 |
DSP1N1GPIO22
0x0 |
DSP1N1GPIO21
0x0 |
DSP1N1GPIO20
0x0 |
DSP1N1GPIO19
0x0 |
DSP1N1GPIO18
0x0 |
DSP1N1GPIO17
0x0 |
DSP1N1GPIO16
0x0 |
DSP1N1GPIO15
0x0 |
DSP1N1GPIO14
0x0 |
DSP1N1GPIO13
0x0 |
DSP1N1GPIO12
0x0 |
DSP1N1GPIO11
0x0 |
DSP1N1GPIO10
0x0 |
DSP1N1GPIO9
0x0 |
DSP1N1GPIO8
0x0 |
DSP1N1GPIO7
0x0 |
DSP1N1GPIO6
0x0 |
DSP1N1GPIO5
0x0 |
DSP1N1GPIO4
0x0 |
DSP1N1GPIO3
0x0 |
DSP1N1GPIO2
0x0 |
DSP1N1GPIO1
0x0 |
DSP1N1GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO31 | RW | GPIO31 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO30 | RW | GPIO30 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO29 | RW | GPIO29 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO28 | RW | GPIO28 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO27 | RW | GPIO27 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO26 | RW | GPIO26 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO25 | RW | GPIO25 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO24 | RW | GPIO24 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO23 | RW | GPIO23 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO22 | RW | GPIO22 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO21 | RW | GPIO21 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO20 | RW | GPIO20 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO19 | RW | GPIO19 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO18 | RW | GPIO18 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO17 | RW | GPIO17 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO16 | RW | GPIO16 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO15 | RW | GPIO15 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO14 | RW | GPIO14 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO13 | RW | GPIO13 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO12 | RW | GPIO12 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO11 | RW | GPIO11 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO10 | RW | GPIO10 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO9 | RW | GPIO9 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO8 | RW | GPIO8 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO7 | RW | GPIO7 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO6 | RW | GPIO6 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO5 | RW | GPIO5 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO4 | RW | GPIO4 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO3 | RW | GPIO3 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO2 | RW | GPIO2 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO1 | RW | GPIO1 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO0 | RW | GPIO0 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010410 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO63
0x0 |
DSP1N1GPIO62
0x0 |
DSP1N1GPIO61
0x0 |
DSP1N1GPIO60
0x0 |
DSP1N1GPIO59
0x0 |
DSP1N1GPIO58
0x0 |
DSP1N1GPIO57
0x0 |
DSP1N1GPIO56
0x0 |
DSP1N1GPIO55
0x0 |
DSP1N1GPIO54
0x0 |
DSP1N1GPIO53
0x0 |
DSP1N1GPIO52
0x0 |
DSP1N1GPIO51
0x0 |
DSP1N1GPIO50
0x0 |
DSP1N1GPIO49
0x0 |
DSP1N1GPIO48
0x0 |
DSP1N1GPIO47
0x0 |
DSP1N1GPIO46
0x0 |
DSP1N1GPIO45
0x0 |
DSP1N1GPIO44
0x0 |
DSP1N1GPIO43
0x0 |
DSP1N1GPIO42
0x0 |
DSP1N1GPIO41
0x0 |
DSP1N1GPIO40
0x0 |
DSP1N1GPIO39
0x0 |
DSP1N1GPIO38
0x0 |
DSP1N1GPIO37
0x0 |
DSP1N1GPIO36
0x0 |
DSP1N1GPIO35
0x0 |
DSP1N1GPIO34
0x0 |
DSP1N1GPIO33
0x0 |
DSP1N1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO63 | RW | GPIO63 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO62 | RW | GPIO62 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO61 | RW | GPIO61 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO60 | RW | GPIO60 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO59 | RW | GPIO59 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO58 | RW | GPIO58 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO57 | RW | GPIO57 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO56 | RW | GPIO56 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO55 | RW | GPIO55 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO54 | RW | GPIO54 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO53 | RW | GPIO53 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO52 | RW | GPIO52 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO51 | RW | GPIO51 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO50 | RW | GPIO50 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO49 | RW | GPIO49 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO48 | RW | GPIO48 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO47 | RW | GPIO47 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO46 | RW | GPIO46 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO45 | RW | GPIO45 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO44 | RW | GPIO44 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO43 | RW | GPIO43 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO42 | RW | GPIO42 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO41 | RW | GPIO41 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO40 | RW | GPIO40 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO39 | RW | GPIO39 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO38 | RW | GPIO38 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO37 | RW | GPIO37 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO36 | RW | GPIO36 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO35 | RW | GPIO35 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO34 | RW | GPIO34 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO33 | RW | GPIO33 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO32 | RW | GPIO32 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010414 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO63
0x0 |
DSP1N1GPIO62
0x0 |
DSP1N1GPIO61
0x0 |
DSP1N1GPIO60
0x0 |
DSP1N1GPIO59
0x0 |
DSP1N1GPIO58
0x0 |
DSP1N1GPIO57
0x0 |
DSP1N1GPIO56
0x0 |
DSP1N1GPIO55
0x0 |
DSP1N1GPIO54
0x0 |
DSP1N1GPIO53
0x0 |
DSP1N1GPIO52
0x0 |
DSP1N1GPIO51
0x0 |
DSP1N1GPIO50
0x0 |
DSP1N1GPIO49
0x0 |
DSP1N1GPIO48
0x0 |
DSP1N1GPIO47
0x0 |
DSP1N1GPIO46
0x0 |
DSP1N1GPIO45
0x0 |
DSP1N1GPIO44
0x0 |
DSP1N1GPIO43
0x0 |
DSP1N1GPIO42
0x0 |
DSP1N1GPIO41
0x0 |
DSP1N1GPIO40
0x0 |
DSP1N1GPIO39
0x0 |
DSP1N1GPIO38
0x0 |
DSP1N1GPIO37
0x0 |
DSP1N1GPIO36
0x0 |
DSP1N1GPIO35
0x0 |
DSP1N1GPIO34
0x0 |
DSP1N1GPIO33
0x0 |
DSP1N1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO63 | RW | GPIO63 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO62 | RW | GPIO62 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO61 | RW | GPIO61 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO60 | RW | GPIO60 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO59 | RW | GPIO59 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO58 | RW | GPIO58 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO57 | RW | GPIO57 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO56 | RW | GPIO56 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO55 | RW | GPIO55 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO54 | RW | GPIO54 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO53 | RW | GPIO53 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO52 | RW | GPIO52 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO51 | RW | GPIO51 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO50 | RW | GPIO50 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO49 | RW | GPIO49 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO48 | RW | GPIO48 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO47 | RW | GPIO47 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO46 | RW | GPIO46 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO45 | RW | GPIO45 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO44 | RW | GPIO44 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO43 | RW | GPIO43 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO42 | RW | GPIO42 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO41 | RW | GPIO41 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO40 | RW | GPIO40 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO39 | RW | GPIO39 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO38 | RW | GPIO38 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO37 | RW | GPIO37 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO36 | RW | GPIO36 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO35 | RW | GPIO35 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO34 | RW | GPIO34 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO33 | RW | GPIO33 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO32 | RW | GPIO32 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010418 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO63
0x0 |
DSP1N1GPIO62
0x0 |
DSP1N1GPIO61
0x0 |
DSP1N1GPIO60
0x0 |
DSP1N1GPIO59
0x0 |
DSP1N1GPIO58
0x0 |
DSP1N1GPIO57
0x0 |
DSP1N1GPIO56
0x0 |
DSP1N1GPIO55
0x0 |
DSP1N1GPIO54
0x0 |
DSP1N1GPIO53
0x0 |
DSP1N1GPIO52
0x0 |
DSP1N1GPIO51
0x0 |
DSP1N1GPIO50
0x0 |
DSP1N1GPIO49
0x0 |
DSP1N1GPIO48
0x0 |
DSP1N1GPIO47
0x0 |
DSP1N1GPIO46
0x0 |
DSP1N1GPIO45
0x0 |
DSP1N1GPIO44
0x0 |
DSP1N1GPIO43
0x0 |
DSP1N1GPIO42
0x0 |
DSP1N1GPIO41
0x0 |
DSP1N1GPIO40
0x0 |
DSP1N1GPIO39
0x0 |
DSP1N1GPIO38
0x0 |
DSP1N1GPIO37
0x0 |
DSP1N1GPIO36
0x0 |
DSP1N1GPIO35
0x0 |
DSP1N1GPIO34
0x0 |
DSP1N1GPIO33
0x0 |
DSP1N1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO63 | RW | GPIO63 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO62 | RW | GPIO62 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO61 | RW | GPIO61 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO60 | RW | GPIO60 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO59 | RW | GPIO59 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO58 | RW | GPIO58 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO57 | RW | GPIO57 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO56 | RW | GPIO56 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO55 | RW | GPIO55 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO54 | RW | GPIO54 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO53 | RW | GPIO53 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO52 | RW | GPIO52 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO51 | RW | GPIO51 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO50 | RW | GPIO50 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO49 | RW | GPIO49 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO48 | RW | GPIO48 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO47 | RW | GPIO47 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO46 | RW | GPIO46 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO45 | RW | GPIO45 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO44 | RW | GPIO44 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO43 | RW | GPIO43 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO42 | RW | GPIO42 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO41 | RW | GPIO41 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO40 | RW | GPIO40 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO39 | RW | GPIO39 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO38 | RW | GPIO38 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO37 | RW | GPIO37 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO36 | RW | GPIO36 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO35 | RW | GPIO35 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO34 | RW | GPIO34 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO33 | RW | GPIO33 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO32 | RW | GPIO32 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x4001041C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO63
0x0 |
DSP1N1GPIO62
0x0 |
DSP1N1GPIO61
0x0 |
DSP1N1GPIO60
0x0 |
DSP1N1GPIO59
0x0 |
DSP1N1GPIO58
0x0 |
DSP1N1GPIO57
0x0 |
DSP1N1GPIO56
0x0 |
DSP1N1GPIO55
0x0 |
DSP1N1GPIO54
0x0 |
DSP1N1GPIO53
0x0 |
DSP1N1GPIO52
0x0 |
DSP1N1GPIO51
0x0 |
DSP1N1GPIO50
0x0 |
DSP1N1GPIO49
0x0 |
DSP1N1GPIO48
0x0 |
DSP1N1GPIO47
0x0 |
DSP1N1GPIO46
0x0 |
DSP1N1GPIO45
0x0 |
DSP1N1GPIO44
0x0 |
DSP1N1GPIO43
0x0 |
DSP1N1GPIO42
0x0 |
DSP1N1GPIO41
0x0 |
DSP1N1GPIO40
0x0 |
DSP1N1GPIO39
0x0 |
DSP1N1GPIO38
0x0 |
DSP1N1GPIO37
0x0 |
DSP1N1GPIO36
0x0 |
DSP1N1GPIO35
0x0 |
DSP1N1GPIO34
0x0 |
DSP1N1GPIO33
0x0 |
DSP1N1GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO63 | RW | GPIO63 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO62 | RW | GPIO62 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO61 | RW | GPIO61 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO60 | RW | GPIO60 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO59 | RW | GPIO59 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO58 | RW | GPIO58 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO57 | RW | GPIO57 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO56 | RW | GPIO56 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO55 | RW | GPIO55 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO54 | RW | GPIO54 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO53 | RW | GPIO53 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO52 | RW | GPIO52 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO51 | RW | GPIO51 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO50 | RW | GPIO50 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO49 | RW | GPIO49 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO48 | RW | GPIO48 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO47 | RW | GPIO47 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO46 | RW | GPIO46 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO45 | RW | GPIO45 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO44 | RW | GPIO44 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO43 | RW | GPIO43 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO42 | RW | GPIO42 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO41 | RW | GPIO41 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO40 | RW | GPIO40 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO39 | RW | GPIO39 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO38 | RW | GPIO38 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO37 | RW | GPIO37 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO36 | RW | GPIO36 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO35 | RW | GPIO35 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO34 | RW | GPIO34 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO33 | RW | GPIO33 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO32 | RW | GPIO32 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010420 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO95
0x0 |
DSP1N1GPIO94
0x0 |
DSP1N1GPIO93
0x0 |
DSP1N1GPIO92
0x0 |
DSP1N1GPIO91
0x0 |
DSP1N1GPIO90
0x0 |
DSP1N1GPIO89
0x0 |
DSP1N1GPIO88
0x0 |
DSP1N1GPIO87
0x0 |
DSP1N1GPIO86
0x0 |
DSP1N1GPIO85
0x0 |
DSP1N1GPIO84
0x0 |
DSP1N1GPIO83
0x0 |
DSP1N1GPIO82
0x0 |
DSP1N1GPIO81
0x0 |
DSP1N1GPIO80
0x0 |
DSP1N1GPIO79
0x0 |
DSP1N1GPIO78
0x0 |
DSP1N1GPIO77
0x0 |
DSP1N1GPIO76
0x0 |
DSP1N1GPIO75
0x0 |
DSP1N1GPIO74
0x0 |
DSP1N1GPIO73
0x0 |
DSP1N1GPIO72
0x0 |
DSP1N1GPIO71
0x0 |
DSP1N1GPIO70
0x0 |
DSP1N1GPIO69
0x0 |
DSP1N1GPIO68
0x0 |
DSP1N1GPIO67
0x0 |
DSP1N1GPIO66
0x0 |
DSP1N1GPIO65
0x0 |
DSP1N1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO95 | RW | GPIO95 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO94 | RW | GPIO94 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO93 | RW | GPIO93 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO92 | RW | GPIO92 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO91 | RW | GPIO91 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO90 | RW | GPIO90 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO89 | RW | GPIO89 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO88 | RW | GPIO88 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO87 | RW | GPIO87 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO86 | RW | GPIO86 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO85 | RW | GPIO85 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO84 | RW | GPIO84 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO83 | RW | GPIO83 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO82 | RW | GPIO82 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO81 | RW | GPIO81 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO80 | RW | GPIO80 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO79 | RW | GPIO79 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO78 | RW | GPIO78 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO77 | RW | GPIO77 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO76 | RW | GPIO76 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO75 | RW | GPIO75 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO74 | RW | GPIO74 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO73 | RW | GPIO73 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO72 | RW | GPIO72 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO71 | RW | GPIO71 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO70 | RW | GPIO70 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO69 | RW | GPIO69 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO68 | RW | GPIO68 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO67 | RW | GPIO67 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO66 | RW | GPIO66 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO65 | RW | GPIO65 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO64 | RW | GPIO64 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010424 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO95
0x0 |
DSP1N1GPIO94
0x0 |
DSP1N1GPIO93
0x0 |
DSP1N1GPIO92
0x0 |
DSP1N1GPIO91
0x0 |
DSP1N1GPIO90
0x0 |
DSP1N1GPIO89
0x0 |
DSP1N1GPIO88
0x0 |
DSP1N1GPIO87
0x0 |
DSP1N1GPIO86
0x0 |
DSP1N1GPIO85
0x0 |
DSP1N1GPIO84
0x0 |
DSP1N1GPIO83
0x0 |
DSP1N1GPIO82
0x0 |
DSP1N1GPIO81
0x0 |
DSP1N1GPIO80
0x0 |
DSP1N1GPIO79
0x0 |
DSP1N1GPIO78
0x0 |
DSP1N1GPIO77
0x0 |
DSP1N1GPIO76
0x0 |
DSP1N1GPIO75
0x0 |
DSP1N1GPIO74
0x0 |
DSP1N1GPIO73
0x0 |
DSP1N1GPIO72
0x0 |
DSP1N1GPIO71
0x0 |
DSP1N1GPIO70
0x0 |
DSP1N1GPIO69
0x0 |
DSP1N1GPIO68
0x0 |
DSP1N1GPIO67
0x0 |
DSP1N1GPIO66
0x0 |
DSP1N1GPIO65
0x0 |
DSP1N1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO95 | RW | GPIO95 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO94 | RW | GPIO94 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO93 | RW | GPIO93 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO92 | RW | GPIO92 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO91 | RW | GPIO91 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO90 | RW | GPIO90 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO89 | RW | GPIO89 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO88 | RW | GPIO88 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO87 | RW | GPIO87 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO86 | RW | GPIO86 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO85 | RW | GPIO85 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO84 | RW | GPIO84 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO83 | RW | GPIO83 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO82 | RW | GPIO82 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO81 | RW | GPIO81 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO80 | RW | GPIO80 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO79 | RW | GPIO79 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO78 | RW | GPIO78 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO77 | RW | GPIO77 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO76 | RW | GPIO76 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO75 | RW | GPIO75 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO74 | RW | GPIO74 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO73 | RW | GPIO73 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO72 | RW | GPIO72 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO71 | RW | GPIO71 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO70 | RW | GPIO70 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO69 | RW | GPIO69 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO68 | RW | GPIO68 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO67 | RW | GPIO67 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO66 | RW | GPIO66 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO65 | RW | GPIO65 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO64 | RW | GPIO64 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010428 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO95
0x0 |
DSP1N1GPIO94
0x0 |
DSP1N1GPIO93
0x0 |
DSP1N1GPIO92
0x0 |
DSP1N1GPIO91
0x0 |
DSP1N1GPIO90
0x0 |
DSP1N1GPIO89
0x0 |
DSP1N1GPIO88
0x0 |
DSP1N1GPIO87
0x0 |
DSP1N1GPIO86
0x0 |
DSP1N1GPIO85
0x0 |
DSP1N1GPIO84
0x0 |
DSP1N1GPIO83
0x0 |
DSP1N1GPIO82
0x0 |
DSP1N1GPIO81
0x0 |
DSP1N1GPIO80
0x0 |
DSP1N1GPIO79
0x0 |
DSP1N1GPIO78
0x0 |
DSP1N1GPIO77
0x0 |
DSP1N1GPIO76
0x0 |
DSP1N1GPIO75
0x0 |
DSP1N1GPIO74
0x0 |
DSP1N1GPIO73
0x0 |
DSP1N1GPIO72
0x0 |
DSP1N1GPIO71
0x0 |
DSP1N1GPIO70
0x0 |
DSP1N1GPIO69
0x0 |
DSP1N1GPIO68
0x0 |
DSP1N1GPIO67
0x0 |
DSP1N1GPIO66
0x0 |
DSP1N1GPIO65
0x0 |
DSP1N1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO95 | RW | GPIO95 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO94 | RW | GPIO94 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO93 | RW | GPIO93 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO92 | RW | GPIO92 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO91 | RW | GPIO91 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO90 | RW | GPIO90 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO89 | RW | GPIO89 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO88 | RW | GPIO88 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO87 | RW | GPIO87 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO86 | RW | GPIO86 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO85 | RW | GPIO85 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO84 | RW | GPIO84 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO83 | RW | GPIO83 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO82 | RW | GPIO82 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO81 | RW | GPIO81 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO80 | RW | GPIO80 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO79 | RW | GPIO79 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO78 | RW | GPIO78 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO77 | RW | GPIO77 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO76 | RW | GPIO76 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO75 | RW | GPIO75 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO74 | RW | GPIO74 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO73 | RW | GPIO73 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO72 | RW | GPIO72 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO71 | RW | GPIO71 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO70 | RW | GPIO70 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO69 | RW | GPIO69 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO68 | RW | GPIO68 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO67 | RW | GPIO67 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO66 | RW | GPIO66 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO65 | RW | GPIO65 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO64 | RW | GPIO64 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x4001042C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO95
0x0 |
DSP1N1GPIO94
0x0 |
DSP1N1GPIO93
0x0 |
DSP1N1GPIO92
0x0 |
DSP1N1GPIO91
0x0 |
DSP1N1GPIO90
0x0 |
DSP1N1GPIO89
0x0 |
DSP1N1GPIO88
0x0 |
DSP1N1GPIO87
0x0 |
DSP1N1GPIO86
0x0 |
DSP1N1GPIO85
0x0 |
DSP1N1GPIO84
0x0 |
DSP1N1GPIO83
0x0 |
DSP1N1GPIO82
0x0 |
DSP1N1GPIO81
0x0 |
DSP1N1GPIO80
0x0 |
DSP1N1GPIO79
0x0 |
DSP1N1GPIO78
0x0 |
DSP1N1GPIO77
0x0 |
DSP1N1GPIO76
0x0 |
DSP1N1GPIO75
0x0 |
DSP1N1GPIO74
0x0 |
DSP1N1GPIO73
0x0 |
DSP1N1GPIO72
0x0 |
DSP1N1GPIO71
0x0 |
DSP1N1GPIO70
0x0 |
DSP1N1GPIO69
0x0 |
DSP1N1GPIO68
0x0 |
DSP1N1GPIO67
0x0 |
DSP1N1GPIO66
0x0 |
DSP1N1GPIO65
0x0 |
DSP1N1GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO95 | RW | GPIO95 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO94 | RW | GPIO94 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO93 | RW | GPIO93 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO92 | RW | GPIO92 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO91 | RW | GPIO91 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO90 | RW | GPIO90 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO89 | RW | GPIO89 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO88 | RW | GPIO88 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO87 | RW | GPIO87 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO86 | RW | GPIO86 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO85 | RW | GPIO85 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO84 | RW | GPIO84 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO83 | RW | GPIO83 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO82 | RW | GPIO82 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO81 | RW | GPIO81 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO80 | RW | GPIO80 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO79 | RW | GPIO79 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO78 | RW | GPIO78 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO77 | RW | GPIO77 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO76 | RW | GPIO76 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO75 | RW | GPIO75 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO74 | RW | GPIO74 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO73 | RW | GPIO73 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO72 | RW | GPIO72 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO71 | RW | GPIO71 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO70 | RW | GPIO70 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO69 | RW | GPIO69 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO68 | RW | GPIO68 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO67 | RW | GPIO67 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO66 | RW | GPIO66 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO65 | RW | GPIO65 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO64 | RW | GPIO64 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010430 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO127
0x0 |
DSP1N1GPIO126
0x0 |
DSP1N1GPIO125
0x0 |
DSP1N1GPIO124
0x0 |
DSP1N1GPIO123
0x0 |
DSP1N1GPIO122
0x0 |
DSP1N1GPIO121
0x0 |
DSP1N1GPIO120
0x0 |
DSP1N1GPIO119
0x0 |
DSP1N1GPIO118
0x0 |
DSP1N1GPIO117
0x0 |
DSP1N1GPIO116
0x0 |
DSP1N1GPIO115
0x0 |
DSP1N1GPIO114
0x0 |
DSP1N1GPIO113
0x0 |
DSP1N1GPIO112
0x0 |
DSP1N1GPIO111
0x0 |
DSP1N1GPIO110
0x0 |
DSP1N1GPIO109
0x0 |
DSP1N1GPIO108
0x0 |
DSP1N1GPIO107
0x0 |
DSP1N1GPIO106
0x0 |
DSP1N1GPIO105
0x0 |
DSP1N1GPIO104
0x0 |
DSP1N1GPIO103
0x0 |
DSP1N1GPIO102
0x0 |
DSP1N1GPIO101
0x0 |
DSP1N1GPIO100
0x0 |
DSP1N1GPIO99
0x0 |
DSP1N1GPIO98
0x0 |
DSP1N1GPIO97
0x0 |
DSP1N1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO127 | RW | GPIO127 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO126 | RW | GPIO126 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO125 | RW | GPIO125 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO124 | RW | GPIO124 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO123 | RW | GPIO123 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO122 | RW | GPIO122 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO121 | RW | GPIO121 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO120 | RW | GPIO120 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO119 | RW | GPIO119 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO118 | RW | GPIO118 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO117 | RW | GPIO117 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO116 | RW | GPIO116 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO115 | RW | GPIO115 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO114 | RW | GPIO114 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO113 | RW | GPIO113 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO112 | RW | GPIO112 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO111 | RW | GPIO111 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO110 | RW | GPIO110 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO109 | RW | GPIO109 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO108 | RW | GPIO108 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO107 | RW | GPIO107 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO106 | RW | GPIO106 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO105 | RW | GPIO105 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO104 | RW | GPIO104 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO103 | RW | GPIO103 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO102 | RW | GPIO102 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO101 | RW | GPIO101 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO100 | RW | GPIO100 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO99 | RW | GPIO99 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO98 | RW | GPIO98 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO97 | RW | GPIO97 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO96 | RW | GPIO96 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010434 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO127
0x0 |
DSP1N1GPIO126
0x0 |
DSP1N1GPIO125
0x0 |
DSP1N1GPIO124
0x0 |
DSP1N1GPIO123
0x0 |
DSP1N1GPIO122
0x0 |
DSP1N1GPIO121
0x0 |
DSP1N1GPIO120
0x0 |
DSP1N1GPIO119
0x0 |
DSP1N1GPIO118
0x0 |
DSP1N1GPIO117
0x0 |
DSP1N1GPIO116
0x0 |
DSP1N1GPIO115
0x0 |
DSP1N1GPIO114
0x0 |
DSP1N1GPIO113
0x0 |
DSP1N1GPIO112
0x0 |
DSP1N1GPIO111
0x0 |
DSP1N1GPIO110
0x0 |
DSP1N1GPIO109
0x0 |
DSP1N1GPIO108
0x0 |
DSP1N1GPIO107
0x0 |
DSP1N1GPIO106
0x0 |
DSP1N1GPIO105
0x0 |
DSP1N1GPIO104
0x0 |
DSP1N1GPIO103
0x0 |
DSP1N1GPIO102
0x0 |
DSP1N1GPIO101
0x0 |
DSP1N1GPIO100
0x0 |
DSP1N1GPIO99
0x0 |
DSP1N1GPIO98
0x0 |
DSP1N1GPIO97
0x0 |
DSP1N1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO127 | RW | GPIO127 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO126 | RW | GPIO126 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO125 | RW | GPIO125 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO124 | RW | GPIO124 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO123 | RW | GPIO123 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO122 | RW | GPIO122 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO121 | RW | GPIO121 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO120 | RW | GPIO120 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO119 | RW | GPIO119 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO118 | RW | GPIO118 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO117 | RW | GPIO117 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO116 | RW | GPIO116 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO115 | RW | GPIO115 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO114 | RW | GPIO114 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO113 | RW | GPIO113 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO112 | RW | GPIO112 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO111 | RW | GPIO111 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO110 | RW | GPIO110 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO109 | RW | GPIO109 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO108 | RW | GPIO108 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO107 | RW | GPIO107 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO106 | RW | GPIO106 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO105 | RW | GPIO105 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO104 | RW | GPIO104 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO103 | RW | GPIO103 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO102 | RW | GPIO102 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO101 | RW | GPIO101 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO100 | RW | GPIO100 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO99 | RW | GPIO99 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO98 | RW | GPIO98 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO97 | RW | GPIO97 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO96 | RW | GPIO96 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x40010438 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO127
0x0 |
DSP1N1GPIO126
0x0 |
DSP1N1GPIO125
0x0 |
DSP1N1GPIO124
0x0 |
DSP1N1GPIO123
0x0 |
DSP1N1GPIO122
0x0 |
DSP1N1GPIO121
0x0 |
DSP1N1GPIO120
0x0 |
DSP1N1GPIO119
0x0 |
DSP1N1GPIO118
0x0 |
DSP1N1GPIO117
0x0 |
DSP1N1GPIO116
0x0 |
DSP1N1GPIO115
0x0 |
DSP1N1GPIO114
0x0 |
DSP1N1GPIO113
0x0 |
DSP1N1GPIO112
0x0 |
DSP1N1GPIO111
0x0 |
DSP1N1GPIO110
0x0 |
DSP1N1GPIO109
0x0 |
DSP1N1GPIO108
0x0 |
DSP1N1GPIO107
0x0 |
DSP1N1GPIO106
0x0 |
DSP1N1GPIO105
0x0 |
DSP1N1GPIO104
0x0 |
DSP1N1GPIO103
0x0 |
DSP1N1GPIO102
0x0 |
DSP1N1GPIO101
0x0 |
DSP1N1GPIO100
0x0 |
DSP1N1GPIO99
0x0 |
DSP1N1GPIO98
0x0 |
DSP1N1GPIO97
0x0 |
DSP1N1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO127 | RW | GPIO127 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO126 | RW | GPIO126 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO125 | RW | GPIO125 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO124 | RW | GPIO124 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO123 | RW | GPIO123 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO122 | RW | GPIO122 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO121 | RW | GPIO121 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO120 | RW | GPIO120 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO119 | RW | GPIO119 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO118 | RW | GPIO118 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO117 | RW | GPIO117 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO116 | RW | GPIO116 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO115 | RW | GPIO115 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO114 | RW | GPIO114 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO113 | RW | GPIO113 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO112 | RW | GPIO112 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO111 | RW | GPIO111 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO110 | RW | GPIO110 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO109 | RW | GPIO109 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO108 | RW | GPIO108 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO107 | RW | GPIO107 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO106 | RW | GPIO106 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO105 | RW | GPIO105 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO104 | RW | GPIO104 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO103 | RW | GPIO103 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO102 | RW | GPIO102 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO101 | RW | GPIO101 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO100 | RW | GPIO100 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO99 | RW | GPIO99 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO98 | RW | GPIO98 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO97 | RW | GPIO97 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO96 | RW | GPIO96 DSP1 N1-priority interrupt. |
| Instance 0 Address: | 0x4001043C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DSP1N1GPIO127
0x0 |
DSP1N1GPIO126
0x0 |
DSP1N1GPIO125
0x0 |
DSP1N1GPIO124
0x0 |
DSP1N1GPIO123
0x0 |
DSP1N1GPIO122
0x0 |
DSP1N1GPIO121
0x0 |
DSP1N1GPIO120
0x0 |
DSP1N1GPIO119
0x0 |
DSP1N1GPIO118
0x0 |
DSP1N1GPIO117
0x0 |
DSP1N1GPIO116
0x0 |
DSP1N1GPIO115
0x0 |
DSP1N1GPIO114
0x0 |
DSP1N1GPIO113
0x0 |
DSP1N1GPIO112
0x0 |
DSP1N1GPIO111
0x0 |
DSP1N1GPIO110
0x0 |
DSP1N1GPIO109
0x0 |
DSP1N1GPIO108
0x0 |
DSP1N1GPIO107
0x0 |
DSP1N1GPIO106
0x0 |
DSP1N1GPIO105
0x0 |
DSP1N1GPIO104
0x0 |
DSP1N1GPIO103
0x0 |
DSP1N1GPIO102
0x0 |
DSP1N1GPIO101
0x0 |
DSP1N1GPIO100
0x0 |
DSP1N1GPIO99
0x0 |
DSP1N1GPIO98
0x0 |
DSP1N1GPIO97
0x0 |
DSP1N1GPIO96
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | DSP1N1GPIO127 | RW | GPIO127 DSP1 N1-priority interrupt. |
| 30 | DSP1N1GPIO126 | RW | GPIO126 DSP1 N1-priority interrupt. |
| 29 | DSP1N1GPIO125 | RW | GPIO125 DSP1 N1-priority interrupt. |
| 28 | DSP1N1GPIO124 | RW | GPIO124 DSP1 N1-priority interrupt. |
| 27 | DSP1N1GPIO123 | RW | GPIO123 DSP1 N1-priority interrupt. |
| 26 | DSP1N1GPIO122 | RW | GPIO122 DSP1 N1-priority interrupt. |
| 25 | DSP1N1GPIO121 | RW | GPIO121 DSP1 N1-priority interrupt. |
| 24 | DSP1N1GPIO120 | RW | GPIO120 DSP1 N1-priority interrupt. |
| 23 | DSP1N1GPIO119 | RW | GPIO119 DSP1 N1-priority interrupt. |
| 22 | DSP1N1GPIO118 | RW | GPIO118 DSP1 N1-priority interrupt. |
| 21 | DSP1N1GPIO117 | RW | GPIO117 DSP1 N1-priority interrupt. |
| 20 | DSP1N1GPIO116 | RW | GPIO116 DSP1 N1-priority interrupt. |
| 19 | DSP1N1GPIO115 | RW | GPIO115 DSP1 N1-priority interrupt. |
| 18 | DSP1N1GPIO114 | RW | GPIO114 DSP1 N1-priority interrupt. |
| 17 | DSP1N1GPIO113 | RW | GPIO113 DSP1 N1-priority interrupt. |
| 16 | DSP1N1GPIO112 | RW | GPIO112 DSP1 N1-priority interrupt. |
| 15 | DSP1N1GPIO111 | RW | GPIO111 DSP1 N1-priority interrupt. |
| 14 | DSP1N1GPIO110 | RW | GPIO110 DSP1 N1-priority interrupt. |
| 13 | DSP1N1GPIO109 | RW | GPIO109 DSP1 N1-priority interrupt. |
| 12 | DSP1N1GPIO108 | RW | GPIO108 DSP1 N1-priority interrupt. |
| 11 | DSP1N1GPIO107 | RW | GPIO107 DSP1 N1-priority interrupt. |
| 10 | DSP1N1GPIO106 | RW | GPIO106 DSP1 N1-priority interrupt. |
| 9 | DSP1N1GPIO105 | RW | GPIO105 DSP1 N1-priority interrupt. |
| 8 | DSP1N1GPIO104 | RW | GPIO104 DSP1 N1-priority interrupt. |
| 7 | DSP1N1GPIO103 | RW | GPIO103 DSP1 N1-priority interrupt. |
| 6 | DSP1N1GPIO102 | RW | GPIO102 DSP1 N1-priority interrupt. |
| 5 | DSP1N1GPIO101 | RW | GPIO101 DSP1 N1-priority interrupt. |
| 4 | DSP1N1GPIO100 | RW | GPIO100 DSP1 N1-priority interrupt. |
| 3 | DSP1N1GPIO99 | RW | GPIO99 DSP1 N1-priority interrupt. |
| 2 | DSP1N1GPIO98 | RW | GPIO98 DSP1 N1-priority interrupt. |
| 1 | DSP1N1GPIO97 | RW | GPIO97 DSP1 N1-priority interrupt. |
| 0 | DSP1N1GPIO96 | RW | GPIO96 DSP1 N1-priority interrupt. |
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